300 lines
10 KiB
C
300 lines
10 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only
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*
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* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _QAIC_H_
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#define _QAIC_H_
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#include <linux/interrupt.h>
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#include <linux/kref.h>
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#include <linux/mhi.h>
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#include <linux/mutex.h>
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#include <linux/pci.h>
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#include <linux/spinlock.h>
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#include <linux/srcu.h>
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#include <linux/wait.h>
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#include <linux/workqueue.h>
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#include <drm/drm_device.h>
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#include <drm/drm_gem.h>
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#define QAIC_DBC_BASE SZ_128K
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#define QAIC_DBC_SIZE SZ_4K
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#define QAIC_NO_PARTITION -1
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#define QAIC_DBC_OFF(i) ((i) * QAIC_DBC_SIZE + QAIC_DBC_BASE)
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#define to_qaic_bo(obj) container_of(obj, struct qaic_bo, base)
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#define to_qaic_drm_device(dev) container_of(dev, struct qaic_drm_device, drm)
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#define to_drm(qddev) (&(qddev)->drm)
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#define to_accel_kdev(qddev) (to_drm(qddev)->accel->kdev) /* Return Linux device of accel node */
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#define to_qaic_device(dev) (to_qaic_drm_device((dev))->qdev)
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enum __packed dev_states {
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/* Device is offline or will be very soon */
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QAIC_OFFLINE,
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/* Device is booting, not clear if it's in a usable state */
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QAIC_BOOT,
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/* Device is fully operational */
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QAIC_ONLINE,
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};
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extern bool datapath_polling;
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struct qaic_user {
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/* Uniquely identifies this user for the device */
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int handle;
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struct kref ref_count;
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/* Char device opened by this user */
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struct qaic_drm_device *qddev;
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/* Node in list of users that opened this drm device */
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struct list_head node;
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/* SRCU used to synchronize this user during cleanup */
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struct srcu_struct qddev_lock;
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atomic_t chunk_id;
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};
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struct dma_bridge_chan {
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/* Pointer to device strcut maintained by driver */
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struct qaic_device *qdev;
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/* ID of this DMA bridge channel(DBC) */
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unsigned int id;
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/* Synchronizes access to xfer_list */
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spinlock_t xfer_lock;
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/* Base address of request queue */
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void *req_q_base;
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/* Base address of response queue */
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void *rsp_q_base;
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/*
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* Base bus address of request queue. Response queue bus address can be
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* calculated by adding request queue size to this variable
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*/
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dma_addr_t dma_addr;
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/* Total size of request and response queue in byte */
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u32 total_size;
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/* Capacity of request/response queue */
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u32 nelem;
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/* The user that opened this DBC */
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struct qaic_user *usr;
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/*
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* Request ID of next memory handle that goes in request queue. One
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* memory handle can enqueue more than one request elements, all
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* this requests that belong to same memory handle have same request ID
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*/
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u16 next_req_id;
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/* true: DBC is in use; false: DBC not in use */
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bool in_use;
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/*
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* Base address of device registers. Used to read/write request and
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* response queue's head and tail pointer of this DBC.
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*/
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void __iomem *dbc_base;
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/* Head of list where each node is a memory handle queued in request queue */
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struct list_head xfer_list;
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/* Synchronizes DBC readers during cleanup */
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struct srcu_struct ch_lock;
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/*
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* When this DBC is released, any thread waiting on this wait queue is
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* woken up
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*/
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wait_queue_head_t dbc_release;
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/* Head of list where each node is a bo associated with this DBC */
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struct list_head bo_lists;
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/* The irq line for this DBC. Used for polling */
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unsigned int irq;
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/* Polling work item to simulate interrupts */
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struct work_struct poll_work;
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};
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struct qaic_device {
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/* Pointer to base PCI device struct of our physical device */
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struct pci_dev *pdev;
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/* Req. ID of request that will be queued next in MHI control device */
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u32 next_seq_num;
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/* Base address of bar 0 */
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void __iomem *bar_0;
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/* Base address of bar 2 */
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void __iomem *bar_2;
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/* Controller structure for MHI devices */
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struct mhi_controller *mhi_cntrl;
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/* MHI control channel device */
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struct mhi_device *cntl_ch;
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/* List of requests queued in MHI control device */
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struct list_head cntl_xfer_list;
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/* Synchronizes MHI control device transactions and its xfer list */
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struct mutex cntl_mutex;
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/* Array of DBC struct of this device */
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struct dma_bridge_chan *dbc;
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/* Work queue for tasks related to MHI control device */
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struct workqueue_struct *cntl_wq;
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/* Synchronizes all the users of device during cleanup */
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struct srcu_struct dev_lock;
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/* Track the state of the device during resets */
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enum dev_states dev_state;
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/* true: single MSI is used to operate device */
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bool single_msi;
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/*
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* true: A tx MHI transaction has failed and a rx buffer is still queued
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* in control device. Such a buffer is considered lost rx buffer
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* false: No rx buffer is lost in control device
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*/
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bool cntl_lost_buf;
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/* Maximum number of DBC supported by this device */
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u32 num_dbc;
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/* Reference to the drm_device for this device when it is created */
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struct qaic_drm_device *qddev;
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/* Generate the CRC of a control message */
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u32 (*gen_crc)(void *msg);
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/* Validate the CRC of a control message */
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bool (*valid_crc)(void *msg);
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/* MHI "QAIC_TIMESYNC" channel device */
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struct mhi_device *qts_ch;
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/* Work queue for tasks related to MHI "QAIC_TIMESYNC" channel */
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struct workqueue_struct *qts_wq;
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};
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struct qaic_drm_device {
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/* The drm device struct of this drm device */
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struct drm_device drm;
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/* Pointer to the root device struct driven by this driver */
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struct qaic_device *qdev;
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/*
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* The physical device can be partition in number of logical devices.
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* And each logical device is given a partition id. This member stores
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* that id. QAIC_NO_PARTITION is a sentinel used to mark that this drm
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* device is the actual physical device
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*/
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s32 partition_id;
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/* Head in list of users who have opened this drm device */
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struct list_head users;
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/* Synchronizes access to users list */
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struct mutex users_mutex;
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};
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struct qaic_bo {
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struct drm_gem_object base;
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/* Scatter/gather table for allocate/imported BO */
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struct sg_table *sgt;
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/* Head in list of slices of this BO */
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struct list_head slices;
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/* Total nents, for all slices of this BO */
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int total_slice_nents;
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/*
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* Direction of transfer. It can assume only two value DMA_TO_DEVICE and
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* DMA_FROM_DEVICE.
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*/
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int dir;
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/* The pointer of the DBC which operates on this BO */
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struct dma_bridge_chan *dbc;
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/* Number of slice that belongs to this buffer */
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u32 nr_slice;
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/* Number of slice that have been transferred by DMA engine */
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u32 nr_slice_xfer_done;
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/*
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* If true then user has attached slicing information to this BO by
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* calling DRM_IOCTL_QAIC_ATTACH_SLICE_BO ioctl.
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*/
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bool sliced;
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/* Request ID of this BO if it is queued for execution */
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u16 req_id;
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/* Handle assigned to this BO */
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u32 handle;
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/* Wait on this for completion of DMA transfer of this BO */
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struct completion xfer_done;
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/*
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* Node in linked list where head is dbc->xfer_list.
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* This link list contain BO's that are queued for DMA transfer.
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*/
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struct list_head xfer_list;
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/*
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* Node in linked list where head is dbc->bo_lists.
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* This link list contain BO's that are associated with the DBC it is
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* linked to.
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*/
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struct list_head bo_list;
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struct {
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/*
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* Latest timestamp(ns) at which kernel received a request to
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* execute this BO
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*/
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u64 req_received_ts;
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/*
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* Latest timestamp(ns) at which kernel enqueued requests of
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* this BO for execution in DMA queue
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*/
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u64 req_submit_ts;
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/*
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* Latest timestamp(ns) at which kernel received a completion
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* interrupt for requests of this BO
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*/
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u64 req_processed_ts;
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/*
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* Number of elements already enqueued in DMA queue before
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* enqueuing requests of this BO
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*/
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u32 queue_level_before;
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} perf_stats;
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/* Synchronizes BO operations */
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struct mutex lock;
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};
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struct bo_slice {
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/* Mapped pages */
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struct sg_table *sgt;
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/* Number of requests required to queue in DMA queue */
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int nents;
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/* See enum dma_data_direction */
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int dir;
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/* Actual requests that will be copied in DMA queue */
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struct dbc_req *reqs;
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struct kref ref_count;
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/* true: No DMA transfer required */
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bool no_xfer;
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/* Pointer to the parent BO handle */
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struct qaic_bo *bo;
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/* Node in list of slices maintained by parent BO */
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struct list_head slice;
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/* Size of this slice in bytes */
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u64 size;
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/* Offset of this slice in buffer */
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u64 offset;
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};
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int get_dbc_req_elem_size(void);
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int get_dbc_rsp_elem_size(void);
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int get_cntl_version(struct qaic_device *qdev, struct qaic_user *usr, u16 *major, u16 *minor);
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int qaic_manage_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
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void qaic_mhi_ul_xfer_cb(struct mhi_device *mhi_dev, struct mhi_result *mhi_result);
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void qaic_mhi_dl_xfer_cb(struct mhi_device *mhi_dev, struct mhi_result *mhi_result);
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int qaic_control_open(struct qaic_device *qdev);
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void qaic_control_close(struct qaic_device *qdev);
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void qaic_release_usr(struct qaic_device *qdev, struct qaic_user *usr);
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irqreturn_t dbc_irq_threaded_fn(int irq, void *data);
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irqreturn_t dbc_irq_handler(int irq, void *data);
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int disable_dbc(struct qaic_device *qdev, u32 dbc_id, struct qaic_user *usr);
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void enable_dbc(struct qaic_device *qdev, u32 dbc_id, struct qaic_user *usr);
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void wakeup_dbc(struct qaic_device *qdev, u32 dbc_id);
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void release_dbc(struct qaic_device *qdev, u32 dbc_id);
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void wake_all_cntl(struct qaic_device *qdev);
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void qaic_dev_reset_clean_local_state(struct qaic_device *qdev);
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struct drm_gem_object *qaic_gem_prime_import(struct drm_device *dev, struct dma_buf *dma_buf);
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int qaic_create_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
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int qaic_mmap_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
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int qaic_attach_slice_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
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int qaic_execute_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
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int qaic_partial_execute_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
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int qaic_wait_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
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int qaic_perf_stats_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
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int qaic_detach_slice_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
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void irq_polling_work(struct work_struct *work);
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#endif /* _QAIC_H_ */
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