183 lines
		
	
	
		
			5.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			183 lines
		
	
	
		
			5.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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| //
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| // This file is provided under a dual BSD/GPLv2 license. When using or
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| // redistributing this file, you may do so under either license.
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| //
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| // Copyright(c) 2022 Advanced Micro Devices, Inc.
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| //
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| // Authors: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
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| //	    Vijendar Mukunda <Vijendar.Mukunda@amd.com>
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| //
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| 
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| /*
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|  * Generic Hardware interface for ACP Audio PDM controller
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|  */
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| 
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| #include <linux/err.h>
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| #include <linux/io.h>
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| #include <linux/module.h>
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| #include <linux/platform_device.h>
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| #include <sound/pcm_params.h>
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| #include <sound/soc.h>
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| #include <sound/soc-dai.h>
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| 
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| #include "amd.h"
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| 
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| #define DRV_NAME "acp-pdm"
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| 
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| static int acp_dmic_prepare(struct snd_pcm_substream *substream,
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| 			    struct snd_soc_dai *dai)
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| {
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| 	struct acp_stream *stream = substream->runtime->private_data;
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| 	struct device *dev = dai->component->dev;
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| 	struct acp_dev_data *adata = dev_get_drvdata(dev);
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| 	u32 physical_addr, size_dmic, period_bytes;
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| 	unsigned int dmic_ctrl;
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| 
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| 	/* Enable default DMIC clk */
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| 	writel(PDM_CLK_FREQ_MASK, adata->acp_base + ACP_WOV_CLK_CTRL);
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| 	dmic_ctrl = readl(adata->acp_base + ACP_WOV_MISC_CTRL);
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| 	dmic_ctrl |= PDM_MISC_CTRL_MASK;
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| 	writel(dmic_ctrl, adata->acp_base + ACP_WOV_MISC_CTRL);
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| 
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| 	period_bytes = frames_to_bytes(substream->runtime,
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| 			substream->runtime->period_size);
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| 	size_dmic = frames_to_bytes(substream->runtime,
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| 			substream->runtime->buffer_size);
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| 
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| 	physical_addr = stream->reg_offset + MEM_WINDOW_START;
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| 
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| 	/* Init DMIC Ring buffer */
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| 	writel(physical_addr, adata->acp_base + ACP_WOV_RX_RINGBUFADDR);
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| 	writel(size_dmic, adata->acp_base + ACP_WOV_RX_RINGBUFSIZE);
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| 	writel(period_bytes, adata->acp_base + ACP_WOV_RX_INTR_WATERMARK_SIZE);
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| 	writel(0x01, adata->acp_base + ACPAXI2AXI_ATU_CTRL);
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| 
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| 	return 0;
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| }
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| 
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| static int acp_dmic_dai_trigger(struct snd_pcm_substream *substream,
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| 				int cmd, struct snd_soc_dai *dai)
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| {
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| 	struct device *dev = dai->component->dev;
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| 	struct acp_dev_data *adata = dev_get_drvdata(dev);
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| 	unsigned int dma_enable;
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| 	int ret = 0;
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| 
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| 	switch (cmd) {
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| 	case SNDRV_PCM_TRIGGER_START:
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| 	case SNDRV_PCM_TRIGGER_RESUME:
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| 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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| 		dma_enable = readl(adata->acp_base + ACP_WOV_PDM_DMA_ENABLE);
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| 		if (!(dma_enable & DMA_EN_MASK)) {
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| 			writel(PDM_ENABLE, adata->acp_base + ACP_WOV_PDM_ENABLE);
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| 			writel(PDM_ENABLE, adata->acp_base + ACP_WOV_PDM_DMA_ENABLE);
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| 		}
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| 
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| 		ret = readl_poll_timeout_atomic(adata->acp_base + ACP_WOV_PDM_DMA_ENABLE,
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| 						dma_enable, (dma_enable & DMA_EN_MASK),
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| 						DELAY_US, PDM_TIMEOUT);
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| 		break;
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| 	case SNDRV_PCM_TRIGGER_STOP:
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| 	case SNDRV_PCM_TRIGGER_SUSPEND:
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| 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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| 		dma_enable = readl(adata->acp_base + ACP_WOV_PDM_DMA_ENABLE);
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| 		if ((dma_enable & DMA_EN_MASK)) {
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| 			writel(PDM_DISABLE, adata->acp_base + ACP_WOV_PDM_ENABLE);
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| 			writel(PDM_DISABLE, adata->acp_base + ACP_WOV_PDM_DMA_ENABLE);
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| 
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| 		}
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| 
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| 		ret = readl_poll_timeout_atomic(adata->acp_base + ACP_WOV_PDM_DMA_ENABLE,
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| 						dma_enable, !(dma_enable & DMA_EN_MASK),
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| 						DELAY_US, PDM_TIMEOUT);
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| 		break;
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| 	default:
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| 		ret = -EINVAL;
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| 		break;
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| 	}
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| 
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| 	return ret;
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| }
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| 
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| static int acp_dmic_hwparams(struct snd_pcm_substream *substream,
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| 			     struct snd_pcm_hw_params *hwparams, struct snd_soc_dai *dai)
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| {
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| 	struct device *dev = dai->component->dev;
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| 	struct acp_dev_data *adata = dev_get_drvdata(dev);
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| 	unsigned int channels, ch_mask;
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| 
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| 	channels = params_channels(hwparams);
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| 	switch (channels) {
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| 	case 2:
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| 		ch_mask = 0;
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| 		break;
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| 	case 4:
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| 		ch_mask = 1;
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| 		break;
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| 	case 6:
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| 		ch_mask = 2;
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| 		break;
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| 	default:
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| 		dev_err(dev, "Invalid channels %d\n", channels);
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| 		return -EINVAL;
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| 	}
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| 
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| 	adata->ch_mask = ch_mask;
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| 	if (params_format(hwparams) != SNDRV_PCM_FORMAT_S32_LE) {
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| 		dev_err(dai->dev, "Invalid format:%d\n", params_format(hwparams));
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| 		return -EINVAL;
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| 	}
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| 
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| 	writel(ch_mask, adata->acp_base + ACP_WOV_PDM_NO_OF_CHANNELS);
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| 	writel(PDM_DEC_64, adata->acp_base + ACP_WOV_PDM_DECIMATION_FACTOR);
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| 
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| 	return 0;
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| }
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| 
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| static int acp_dmic_dai_startup(struct snd_pcm_substream *substream,
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| 				struct snd_soc_dai *dai)
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| {
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| 	struct acp_stream *stream = substream->runtime->private_data;
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| 	struct device *dev = dai->component->dev;
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| 	struct acp_dev_data *adata = dev_get_drvdata(dev);
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| 	u32 ext_int_ctrl;
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| 
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| 	stream->dai_id = DMIC_INSTANCE;
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| 	stream->irq_bit = BIT(PDM_DMA_STAT);
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| 	stream->pte_offset = ACP_SRAM_PDM_PTE_OFFSET;
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| 	stream->reg_offset = ACP_REGION2_OFFSET;
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| 
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| 	/* Enable DMIC Interrupts */
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| 	ext_int_ctrl = readl(ACP_EXTERNAL_INTR_CNTL(adata, 0));
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| 	ext_int_ctrl |= PDM_DMA_INTR_MASK;
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| 	writel(ext_int_ctrl, ACP_EXTERNAL_INTR_CNTL(adata, 0));
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| 
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| 	return 0;
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| }
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| 
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| static void acp_dmic_dai_shutdown(struct snd_pcm_substream *substream,
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| 				  struct snd_soc_dai *dai)
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| {
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| 	struct device *dev = dai->component->dev;
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| 	struct acp_dev_data *adata = dev_get_drvdata(dev);
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| 	u32 ext_int_ctrl;
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| 
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| 	/* Disable DMIC interrupts */
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| 	ext_int_ctrl = readl(ACP_EXTERNAL_INTR_CNTL(adata, 0));
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| 	ext_int_ctrl &= ~PDM_DMA_INTR_MASK;
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| 	writel(ext_int_ctrl, ACP_EXTERNAL_INTR_CNTL(adata, 0));
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| }
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| 
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| const struct snd_soc_dai_ops acp_dmic_dai_ops = {
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| 	.prepare	= acp_dmic_prepare,
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| 	.hw_params	= acp_dmic_hwparams,
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| 	.trigger	= acp_dmic_dai_trigger,
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| 	.startup	= acp_dmic_dai_startup,
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| 	.shutdown	= acp_dmic_dai_shutdown,
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| };
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| EXPORT_SYMBOL_GPL(acp_dmic_dai_ops);
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| 
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| MODULE_LICENSE("Dual BSD/GPL");
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| MODULE_ALIAS(DRV_NAME);
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