217 lines
6.9 KiB
C
217 lines
6.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* The driver for the Cirrus Logic's Sound Fusion CS46XX based soundcards
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* Copyright (c) by Jaroslav Kysela <perex@perex.cz>
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*/
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/*
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* 2002-07 Benny Sjostrand benny@hostmobility.com
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*/
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#ifdef CONFIG_SND_CS46XX_NEW_DSP /* hack ... */
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#ifndef __DSP_SPOS_H__
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#define __DSP_SPOS_H__
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#define DSP_MAX_SYMBOLS 1024
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#define DSP_MAX_MODULES 64
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#define DSP_CODE_BYTE_SIZE 0x00007000UL
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#define DSP_PARAMETER_BYTE_SIZE 0x00003000UL
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#define DSP_SAMPLE_BYTE_SIZE 0x00003800UL
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#define DSP_PARAMETER_BYTE_OFFSET 0x00000000UL
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#define DSP_SAMPLE_BYTE_OFFSET 0x00010000UL
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#define DSP_CODE_BYTE_OFFSET 0x00020000UL
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#define WIDE_INSTR_MASK 0x0040
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#define WIDE_LADD_INSTR_MASK 0x0380
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/* this instruction types
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needs to be reallocated when load
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code into DSP */
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enum wide_opcode {
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WIDE_FOR_BEGIN_LOOP = 0x20,
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WIDE_FOR_BEGIN_LOOP2,
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WIDE_COND_GOTO_ADDR = 0x30,
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WIDE_COND_GOTO_CALL,
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WIDE_TBEQ_COND_GOTO_ADDR = 0x70,
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WIDE_TBEQ_COND_CALL_ADDR,
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WIDE_TBEQ_NCOND_GOTO_ADDR,
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WIDE_TBEQ_NCOND_CALL_ADDR,
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WIDE_TBEQ_COND_GOTO1_ADDR,
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WIDE_TBEQ_COND_CALL1_ADDR,
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WIDE_TBEQ_NCOND_GOTOI_ADDR,
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WIDE_TBEQ_NCOND_CALL1_ADDR,
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};
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/* SAMPLE segment */
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#define VARI_DECIMATE_BUF1 0x0000
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#define WRITE_BACK_BUF1 0x0400
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#define CODEC_INPUT_BUF1 0x0500
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#define PCM_READER_BUF1 0x0600
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#define SRC_DELAY_BUF1 0x0680
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#define VARI_DECIMATE_BUF0 0x0780
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#define SRC_OUTPUT_BUF1 0x07A0
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#define ASYNC_IP_OUTPUT_BUFFER1 0x0A00
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#define OUTPUT_SNOOP_BUFFER 0x0B00
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#define SPDIFI_IP_OUTPUT_BUFFER1 0x0E00
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#define SPDIFO_IP_OUTPUT_BUFFER1 0x1000
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#define MIX_SAMPLE_BUF1 0x1400
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#define MIX_SAMPLE_BUF2 0x2E80
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#define MIX_SAMPLE_BUF3 0x2F00
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#define MIX_SAMPLE_BUF4 0x2F80
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#define MIX_SAMPLE_BUF5 0x3000
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/* Task stack address */
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#define HFG_STACK 0x066A
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#define FG_STACK 0x066E
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#define BG_STACK 0x068E
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/* SCB's addresses */
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#define SPOSCB_ADDR 0x070
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#define BG_TREE_SCB_ADDR 0x635
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#define NULL_SCB_ADDR 0x000
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#define TIMINGMASTER_SCB_ADDR 0x010
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#define CODECOUT_SCB_ADDR 0x020
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#define PCMREADER_SCB_ADDR 0x030
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#define WRITEBACK_SCB_ADDR 0x040
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#define CODECIN_SCB_ADDR 0x080
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#define MASTERMIX_SCB_ADDR 0x090
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#define SRCTASK_SCB_ADDR 0x0A0
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#define VARIDECIMATE_SCB_ADDR 0x0B0
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#define PCMSERIALIN_SCB_ADDR 0x0C0
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#define FG_TASK_HEADER_ADDR 0x600
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#define ASYNCTX_SCB_ADDR 0x0E0
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#define ASYNCRX_SCB_ADDR 0x0F0
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#define SRCTASKII_SCB_ADDR 0x100
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#define OUTPUTSNOOP_SCB_ADDR 0x110
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#define PCMSERIALINII_SCB_ADDR 0x120
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#define SPIOWRITE_SCB_ADDR 0x130
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#define REAR_CODECOUT_SCB_ADDR 0x140
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#define OUTPUTSNOOPII_SCB_ADDR 0x150
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#define PCMSERIALIN_PCM_SCB_ADDR 0x160
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#define RECORD_MIXER_SCB_ADDR 0x170
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#define REAR_MIXER_SCB_ADDR 0x180
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#define CLFE_MIXER_SCB_ADDR 0x190
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#define CLFE_CODEC_SCB_ADDR 0x1A0
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/* hyperforground SCB's*/
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#define HFG_TREE_SCB 0xBA0
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#define SPDIFI_SCB_INST 0xBB0
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#define SPDIFO_SCB_INST 0xBC0
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#define WRITE_BACK_SPB 0x0D0
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/* offsets */
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#define AsyncCIOFIFOPointer 0xd
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#define SPDIFOFIFOPointer 0xd
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#define SPDIFIFIFOPointer 0xd
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#define TCBData 0xb
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#define HFGFlags 0xa
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#define TCBContextBlk 0x10
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#define AFGTxAccumPhi 0x4
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#define SCBsubListPtr 0x9
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#define SCBfuncEntryPtr 0xA
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#define SRCCorPerGof 0x2
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#define SRCPhiIncr6Int26Frac 0xd
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#define SCBVolumeCtrl 0xe
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/* conf */
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#define UseASER1Input 1
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/*
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* The following defines are for the flags in the rsConfig01/23 registers of
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* the SP.
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*/
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#define RSCONFIG_MODULO_SIZE_MASK 0x0000000FL
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#define RSCONFIG_MODULO_16 0x00000001L
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#define RSCONFIG_MODULO_32 0x00000002L
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#define RSCONFIG_MODULO_64 0x00000003L
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#define RSCONFIG_MODULO_128 0x00000004L
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#define RSCONFIG_MODULO_256 0x00000005L
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#define RSCONFIG_MODULO_512 0x00000006L
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#define RSCONFIG_MODULO_1024 0x00000007L
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#define RSCONFIG_MODULO_4 0x00000008L
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#define RSCONFIG_MODULO_8 0x00000009L
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#define RSCONFIG_SAMPLE_SIZE_MASK 0x000000C0L
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#define RSCONFIG_SAMPLE_8MONO 0x00000000L
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#define RSCONFIG_SAMPLE_8STEREO 0x00000040L
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#define RSCONFIG_SAMPLE_16MONO 0x00000080L
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#define RSCONFIG_SAMPLE_16STEREO 0x000000C0L
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#define RSCONFIG_UNDERRUN_ZERO 0x00004000L
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#define RSCONFIG_DMA_TO_HOST 0x00008000L
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#define RSCONFIG_STREAM_NUM_MASK 0x00FF0000L
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#define RSCONFIG_MAX_DMA_SIZE_MASK 0x1F000000L
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#define RSCONFIG_DMA_ENABLE 0x20000000L
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#define RSCONFIG_PRIORITY_MASK 0xC0000000L
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#define RSCONFIG_PRIORITY_HIGH 0x00000000L
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#define RSCONFIG_PRIORITY_MEDIUM_HIGH 0x40000000L
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#define RSCONFIG_PRIORITY_MEDIUM_LOW 0x80000000L
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#define RSCONFIG_PRIORITY_LOW 0xC0000000L
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#define RSCONFIG_STREAM_NUM_SHIFT 16L
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#define RSCONFIG_MAX_DMA_SIZE_SHIFT 24L
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/* SP constants */
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#define FG_INTERVAL_TIMER_PERIOD 0x0051
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#define BG_INTERVAL_TIMER_PERIOD 0x0100
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/* Only SP accessible registers */
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#define SP_ASER_COUNTDOWN 0x8040
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#define SP_SPDOUT_FIFO 0x0108
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#define SP_SPDIN_MI_FIFO 0x01E0
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#define SP_SPDIN_D_FIFO 0x01F0
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#define SP_SPDIN_STATUS 0x8048
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#define SP_SPDIN_CONTROL 0x8049
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#define SP_SPDIN_FIFOPTR 0x804A
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#define SP_SPDOUT_STATUS 0x804C
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#define SP_SPDOUT_CONTROL 0x804D
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#define SP_SPDOUT_CSUV 0x808E
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static inline u8 _wrap_all_bits (u8 val)
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{
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u8 wrapped;
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/* wrap all 8 bits */
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wrapped =
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((val & 0x1 ) << 7) |
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((val & 0x2 ) << 5) |
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((val & 0x4 ) << 3) |
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((val & 0x8 ) << 1) |
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((val & 0x10) >> 1) |
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((val & 0x20) >> 3) |
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((val & 0x40) >> 5) |
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((val & 0x80) >> 7);
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return wrapped;
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}
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static inline void cs46xx_dsp_spos_update_scb (struct snd_cs46xx * chip,
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struct dsp_scb_descriptor * scb)
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{
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/* update nextSCB and subListPtr in SCB */
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snd_cs46xx_poke(chip,
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(scb->address + SCBsubListPtr) << 2,
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(scb->sub_list_ptr->address << 0x10) |
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(scb->next_scb_ptr->address));
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scb->updated = 1;
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}
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static inline void cs46xx_dsp_scb_set_volume (struct snd_cs46xx * chip,
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struct dsp_scb_descriptor * scb,
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u16 left, u16 right)
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{
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unsigned int val = ((0xffff - left) << 16 | (0xffff - right));
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snd_cs46xx_poke(chip, (scb->address + SCBVolumeCtrl) << 2, val);
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snd_cs46xx_poke(chip, (scb->address + SCBVolumeCtrl + 1) << 2, val);
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scb->volume_set = 1;
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scb->volume[0] = left;
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scb->volume[1] = right;
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}
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#endif /* __DSP_SPOS_H__ */
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#endif /* CONFIG_SND_CS46XX_NEW_DSP */
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