379 lines
10 KiB
C
379 lines
10 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "priv.h"
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#include "chan.h"
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#include "head.h"
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#include "ior.h"
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#include <subdev/timer.h>
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#include <nvif/class.h>
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void
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g94_sor_dp_watermark(struct nvkm_ior *sor, int head, u8 watermark)
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{
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struct nvkm_device *device = sor->disp->engine.subdev.device;
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const u32 loff = nv50_sor_link(sor);
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nvkm_mask(device, 0x61c128 + loff, 0x0000003f, watermark);
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}
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void
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g94_sor_dp_activesym(struct nvkm_ior *sor, int head,
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u8 TU, u8 VTUa, u8 VTUf, u8 VTUi)
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{
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struct nvkm_device *device = sor->disp->engine.subdev.device;
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const u32 loff = nv50_sor_link(sor);
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nvkm_mask(device, 0x61c10c + loff, 0x000001fc, TU << 2);
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nvkm_mask(device, 0x61c128 + loff, 0x010f7f00, VTUa << 24 | VTUf << 16 | VTUi << 8);
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}
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void
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g94_sor_dp_audio_sym(struct nvkm_ior *sor, int head, u16 h, u32 v)
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{
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struct nvkm_device *device = sor->disp->engine.subdev.device;
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const u32 soff = nv50_ior_base(sor);
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nvkm_mask(device, 0x61c1e8 + soff, 0x0000ffff, h);
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nvkm_mask(device, 0x61c1ec + soff, 0x00ffffff, v);
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}
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void
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g94_sor_dp_drive(struct nvkm_ior *sor, int ln, int pc, int dc, int pe, int pu)
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{
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struct nvkm_device *device = sor->disp->engine.subdev.device;
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const u32 loff = nv50_sor_link(sor);
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const u32 shift = sor->func->dp->lanes[ln] * 8;
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u32 data[3];
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data[0] = nvkm_rd32(device, 0x61c118 + loff) & ~(0x000000ff << shift);
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data[1] = nvkm_rd32(device, 0x61c120 + loff) & ~(0x000000ff << shift);
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data[2] = nvkm_rd32(device, 0x61c130 + loff);
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if ((data[2] & 0x0000ff00) < (pu << 8) || ln == 0)
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data[2] = (data[2] & ~0x0000ff00) | (pu << 8);
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nvkm_wr32(device, 0x61c118 + loff, data[0] | (dc << shift));
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nvkm_wr32(device, 0x61c120 + loff, data[1] | (pe << shift));
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nvkm_wr32(device, 0x61c130 + loff, data[2]);
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}
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void
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g94_sor_dp_pattern(struct nvkm_ior *sor, int pattern)
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{
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struct nvkm_device *device = sor->disp->engine.subdev.device;
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const u32 loff = nv50_sor_link(sor);
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u32 data;
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switch (pattern) {
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case 0: data = 0x00001000; break;
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case 1: data = 0x01000000; break;
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case 2: data = 0x02000000; break;
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default:
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WARN_ON(1);
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return;
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}
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nvkm_mask(device, 0x61c10c + loff, 0x0f001000, data);
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}
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void
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g94_sor_dp_power(struct nvkm_ior *sor, int nr)
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{
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struct nvkm_device *device = sor->disp->engine.subdev.device;
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const u32 soff = nv50_ior_base(sor);
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const u32 loff = nv50_sor_link(sor);
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u32 mask = 0, i;
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for (i = 0; i < nr; i++)
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mask |= 1 << sor->func->dp->lanes[i];
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nvkm_mask(device, 0x61c130 + loff, 0x0000000f, mask);
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nvkm_mask(device, 0x61c034 + soff, 0x80000000, 0x80000000);
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nvkm_msec(device, 2000,
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if (!(nvkm_rd32(device, 0x61c034 + soff) & 0x80000000))
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break;
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);
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}
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int
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g94_sor_dp_links(struct nvkm_ior *sor, struct nvkm_i2c_aux *aux)
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{
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struct nvkm_device *device = sor->disp->engine.subdev.device;
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const u32 soff = nv50_ior_base(sor);
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const u32 loff = nv50_sor_link(sor);
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u32 dpctrl = 0x00000000;
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u32 clksor = 0x00000000;
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dpctrl |= ((1 << sor->dp.nr) - 1) << 16;
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if (sor->dp.ef)
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dpctrl |= 0x00004000;
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if (sor->dp.bw > 0x06)
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clksor |= 0x00040000;
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nvkm_mask(device, 0x614300 + soff, 0x000c0000, clksor);
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nvkm_mask(device, 0x61c10c + loff, 0x001f4000, dpctrl);
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return 0;
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}
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const struct nvkm_ior_func_dp
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g94_sor_dp = {
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.lanes = { 2, 1, 0, 3},
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.links = g94_sor_dp_links,
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.power = g94_sor_dp_power,
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.pattern = g94_sor_dp_pattern,
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.drive = g94_sor_dp_drive,
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.audio_sym = g94_sor_dp_audio_sym,
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.activesym = g94_sor_dp_activesym,
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.watermark = g94_sor_dp_watermark,
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};
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static bool
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g94_sor_war_needed(struct nvkm_ior *sor)
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{
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struct nvkm_device *device = sor->disp->engine.subdev.device;
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const u32 soff = nv50_ior_base(sor);
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if (sor->asy.proto == TMDS) {
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switch (nvkm_rd32(device, 0x614300 + soff) & 0x00030000) {
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case 0x00000000:
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case 0x00030000:
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return true;
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default:
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break;
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}
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}
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return false;
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}
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static void
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g94_sor_war_update_sppll1(struct nvkm_disp *disp)
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{
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struct nvkm_device *device = disp->engine.subdev.device;
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struct nvkm_ior *ior;
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bool used = false;
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u32 clksor;
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list_for_each_entry(ior, &disp->iors, head) {
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if (ior->type != SOR)
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continue;
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clksor = nvkm_rd32(device, 0x614300 + nv50_ior_base(ior));
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switch (clksor & 0x03000000) {
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case 0x02000000:
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case 0x03000000:
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used = true;
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break;
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default:
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break;
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}
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}
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if (used)
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return;
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nvkm_mask(device, 0x00e840, 0x80000000, 0x00000000);
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}
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static void
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g94_sor_war_3(struct nvkm_ior *sor)
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{
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struct nvkm_device *device = sor->disp->engine.subdev.device;
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const u32 soff = nv50_ior_base(sor);
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u32 sorpwr;
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if (!g94_sor_war_needed(sor))
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return;
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sorpwr = nvkm_rd32(device, 0x61c004 + soff);
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if (sorpwr & 0x00000001) {
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u32 seqctl = nvkm_rd32(device, 0x61c030 + soff);
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u32 pd_pc = (seqctl & 0x00000f00) >> 8;
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u32 pu_pc = seqctl & 0x0000000f;
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nvkm_wr32(device, 0x61c040 + soff + pd_pc * 4, 0x1f008000);
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nvkm_msec(device, 2000,
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if (!(nvkm_rd32(device, 0x61c030 + soff) & 0x10000000))
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break;
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);
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nvkm_mask(device, 0x61c004 + soff, 0x80000001, 0x80000000);
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nvkm_msec(device, 2000,
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if (!(nvkm_rd32(device, 0x61c030 + soff) & 0x10000000))
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break;
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);
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nvkm_wr32(device, 0x61c040 + soff + pd_pc * 4, 0x00002000);
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nvkm_wr32(device, 0x61c040 + soff + pu_pc * 4, 0x1f000000);
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}
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nvkm_mask(device, 0x61c10c + soff, 0x00000001, 0x00000000);
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nvkm_mask(device, 0x614300 + soff, 0x03000000, 0x00000000);
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if (sorpwr & 0x00000001)
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nvkm_mask(device, 0x61c004 + soff, 0x80000001, 0x80000001);
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g94_sor_war_update_sppll1(sor->disp);
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}
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static void
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g94_sor_war_2(struct nvkm_ior *sor)
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{
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struct nvkm_device *device = sor->disp->engine.subdev.device;
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const u32 soff = nv50_ior_base(sor);
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if (!g94_sor_war_needed(sor))
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return;
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nvkm_mask(device, 0x00e840, 0x80000000, 0x80000000);
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nvkm_mask(device, 0x614300 + soff, 0x03000000, 0x03000000);
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nvkm_mask(device, 0x61c10c + soff, 0x00000001, 0x00000001);
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nvkm_mask(device, 0x61c00c + soff, 0x0f000000, 0x00000000);
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nvkm_mask(device, 0x61c008 + soff, 0xff000000, 0x14000000);
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nvkm_usec(device, 400, NVKM_DELAY);
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nvkm_mask(device, 0x61c008 + soff, 0xff000000, 0x00000000);
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nvkm_mask(device, 0x61c00c + soff, 0x0f000000, 0x01000000);
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if (nvkm_rd32(device, 0x61c004 + soff) & 0x00000001) {
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u32 seqctl = nvkm_rd32(device, 0x61c030 + soff);
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u32 pu_pc = seqctl & 0x0000000f;
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nvkm_wr32(device, 0x61c040 + soff + pu_pc * 4, 0x1f008000);
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}
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}
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void
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g94_sor_state(struct nvkm_ior *sor, struct nvkm_ior_state *state)
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{
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struct nvkm_device *device = sor->disp->engine.subdev.device;
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const u32 coff = sor->id * 8 + (state == &sor->arm) * 4;
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u32 ctrl = nvkm_rd32(device, 0x610794 + coff);
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state->proto_evo = (ctrl & 0x00000f00) >> 8;
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switch (state->proto_evo) {
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case 0: state->proto = LVDS; state->link = 1; break;
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case 1: state->proto = TMDS; state->link = 1; break;
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case 2: state->proto = TMDS; state->link = 2; break;
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case 5: state->proto = TMDS; state->link = 3; break;
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case 8: state->proto = DP; state->link = 1; break;
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case 9: state->proto = DP; state->link = 2; break;
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default:
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state->proto = UNKNOWN;
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break;
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}
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state->head = ctrl & 0x00000003;
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nv50_pior_depth(sor, state, ctrl);
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}
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static const struct nvkm_ior_func
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g94_sor = {
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.state = g94_sor_state,
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.power = nv50_sor_power,
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.clock = nv50_sor_clock,
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.war_2 = g94_sor_war_2,
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.war_3 = g94_sor_war_3,
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.hdmi = &g84_sor_hdmi,
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.dp = &g94_sor_dp,
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};
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static int
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g94_sor_new(struct nvkm_disp *disp, int id)
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{
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return nvkm_ior_new_(&g94_sor, disp, SOR, id, false);
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}
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int
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g94_sor_cnt(struct nvkm_disp *disp, unsigned long *pmask)
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{
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struct nvkm_device *device = disp->engine.subdev.device;
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*pmask = (nvkm_rd32(device, 0x610184) & 0x0f000000) >> 24;
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return 4;
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}
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static const struct nvkm_disp_mthd_list
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g94_disp_core_mthd_sor = {
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.mthd = 0x0040,
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.addr = 0x000008,
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.data = {
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{ 0x0600, 0x610794 },
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{}
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}
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};
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const struct nvkm_disp_chan_mthd
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g94_disp_core_mthd = {
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.name = "Core",
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.addr = 0x000000,
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.prev = 0x000004,
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.data = {
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{ "Global", 1, &nv50_disp_core_mthd_base },
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{ "DAC", 3, &g84_disp_core_mthd_dac },
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{ "SOR", 4, &g94_disp_core_mthd_sor },
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{ "PIOR", 3, &nv50_disp_core_mthd_pior },
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{ "HEAD", 2, &g84_disp_core_mthd_head },
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{}
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}
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};
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const struct nvkm_disp_chan_user
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g94_disp_core = {
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.func = &nv50_disp_core_func,
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.ctrl = 0,
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.user = 0,
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.mthd = &g94_disp_core_mthd,
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};
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static const struct nvkm_disp_func
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g94_disp = {
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.oneinit = nv50_disp_oneinit,
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.init = nv50_disp_init,
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.fini = nv50_disp_fini,
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.intr = nv50_disp_intr,
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.super = nv50_disp_super,
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.uevent = &nv50_disp_chan_uevent,
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.head = { .cnt = nv50_head_cnt, .new = nv50_head_new },
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.dac = { .cnt = nv50_dac_cnt, .new = nv50_dac_new },
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.sor = { .cnt = g94_sor_cnt, .new = g94_sor_new },
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.pior = { .cnt = nv50_pior_cnt, .new = nv50_pior_new },
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.root = { 0,0,GT206_DISP },
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.user = {
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{{0,0, G82_DISP_CURSOR }, nvkm_disp_chan_new, & nv50_disp_curs },
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{{0,0, G82_DISP_OVERLAY }, nvkm_disp_chan_new, & nv50_disp_oimm },
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{{0,0,GT200_DISP_BASE_CHANNEL_DMA }, nvkm_disp_chan_new, & g84_disp_base },
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{{0,0,GT206_DISP_CORE_CHANNEL_DMA }, nvkm_disp_core_new, & g94_disp_core },
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{{0,0,GT200_DISP_OVERLAY_CHANNEL_DMA}, nvkm_disp_chan_new, >200_disp_ovly },
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{}
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},
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};
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int
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g94_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
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struct nvkm_disp **pdisp)
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{
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return nvkm_disp_new_(&g94_disp, device, type, inst, pdisp);
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}
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