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				| tests | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| altera-cvp.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| altera-fpga2sdram.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| altera-freeze-bridge.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| altera-hps2fpga.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| altera-pr-ip-core-plat.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| altera-pr-ip-core.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| altera-ps-spi.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| dfl-afu-dma-region.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| dfl-afu-error.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| dfl-afu-main.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| dfl-afu-region.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| dfl-afu.h | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| dfl-fme-br.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| dfl-fme-error.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| dfl-fme-main.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| dfl-fme-mgr.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| dfl-fme-perf.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| dfl-fme-pr.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| dfl-fme-pr.h | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| dfl-fme-region.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| dfl-fme.h | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| dfl-n3000-nios.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| dfl-pci.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| dfl.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| dfl.h | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| fpga-bridge.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| fpga-mgr.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| fpga-region.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| ice40-spi.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| intel-m10-bmc-sec-update.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| Kconfig | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| lattice-sysconfig-spi.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| lattice-sysconfig.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| lattice-sysconfig.h | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| machxo2-spi.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| Makefile | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| microchip-spi.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| of-fpga-region.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| socfpga-a10.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| socfpga.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| stratix10-soc.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| ts73xx-fpga.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| versal-fpga.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| xilinx-core.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| xilinx-core.h | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| xilinx-pr-decoupler.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| xilinx-selectmap.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| xilinx-spi.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| zynq-fpga.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 | 
		
			
			
			
			
				| zynqmp-fpga.c | Initial import of 6.12.0-55.20.1.el10_0 | 2025-07-14 21:26:21 +00:00 |