306 lines
7.6 KiB
C
306 lines
7.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
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/*
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* Copyright 2018-2023 Amazon.com, Inc. or its affiliates. All rights reserved.
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*/
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#ifndef _EFA_IO_H_
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#define _EFA_IO_H_
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#define EFA_IO_TX_DESC_NUM_BUFS 2
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#define EFA_IO_TX_DESC_NUM_RDMA_BUFS 1
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#define EFA_IO_TX_DESC_INLINE_MAX_SIZE 32
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#define EFA_IO_TX_DESC_IMM_DATA_SIZE 4
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enum efa_io_queue_type {
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/* send queue (of a QP) */
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EFA_IO_SEND_QUEUE = 1,
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/* recv queue (of a QP) */
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EFA_IO_RECV_QUEUE = 2,
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};
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enum efa_io_send_op_type {
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/* send message */
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EFA_IO_SEND = 0,
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/* RDMA read */
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EFA_IO_RDMA_READ = 1,
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/* RDMA write */
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EFA_IO_RDMA_WRITE = 2,
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};
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enum efa_io_comp_status {
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/* Successful completion */
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EFA_IO_COMP_STATUS_OK = 0,
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/* Flushed during QP destroy */
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EFA_IO_COMP_STATUS_FLUSHED = 1,
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/* Internal QP error */
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EFA_IO_COMP_STATUS_LOCAL_ERROR_QP_INTERNAL_ERROR = 2,
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/* Bad operation type */
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EFA_IO_COMP_STATUS_LOCAL_ERROR_INVALID_OP_TYPE = 3,
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/* Bad AH */
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EFA_IO_COMP_STATUS_LOCAL_ERROR_INVALID_AH = 4,
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/* LKEY not registered or does not match IOVA */
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EFA_IO_COMP_STATUS_LOCAL_ERROR_INVALID_LKEY = 5,
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/* Message too long */
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EFA_IO_COMP_STATUS_LOCAL_ERROR_BAD_LENGTH = 6,
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/* Destination ENI is down or does not run EFA */
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EFA_IO_COMP_STATUS_REMOTE_ERROR_BAD_ADDRESS = 7,
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/* Connection was reset by remote side */
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EFA_IO_COMP_STATUS_REMOTE_ERROR_ABORT = 8,
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/* Bad dest QP number (QP does not exist or is in error state) */
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EFA_IO_COMP_STATUS_REMOTE_ERROR_BAD_DEST_QPN = 9,
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/* Destination resource not ready (no WQEs posted on RQ) */
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EFA_IO_COMP_STATUS_REMOTE_ERROR_RNR = 10,
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/* Receiver SGL too short */
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EFA_IO_COMP_STATUS_REMOTE_ERROR_BAD_LENGTH = 11,
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/* Unexpected status returned by responder */
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EFA_IO_COMP_STATUS_REMOTE_ERROR_BAD_STATUS = 12,
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/* Unresponsive remote - detected locally */
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EFA_IO_COMP_STATUS_LOCAL_ERROR_UNRESP_REMOTE = 13,
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};
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struct efa_io_tx_meta_desc {
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/* Verbs-generated Request ID */
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u16 req_id;
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/*
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* control flags
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* 3:0 : op_type - enum efa_io_send_op_type
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* 4 : has_imm - immediate_data field carries valid
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* data.
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* 5 : inline_msg - inline mode - inline message data
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* follows this descriptor (no buffer descriptors).
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* Note that it is different from immediate data
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* 6 : meta_extension - Extended metadata. MBZ
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* 7 : meta_desc - Indicates metadata descriptor.
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* Must be set.
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*/
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u8 ctrl1;
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/*
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* control flags
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* 0 : phase
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* 1 : reserved25 - MBZ
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* 2 : first - Indicates first descriptor in
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* transaction. Must be set.
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* 3 : last - Indicates last descriptor in
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* transaction. Must be set.
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* 4 : comp_req - Indicates whether completion should
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* be posted, after packet is transmitted. Valid only
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* for the first descriptor
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* 7:5 : reserved29 - MBZ
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*/
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u8 ctrl2;
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u16 dest_qp_num;
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/*
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* If inline_msg bit is set, length of inline message in bytes,
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* otherwise length of SGL (number of buffers).
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*/
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u16 length;
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/*
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* immediate data: if has_imm is set, then this field is included
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* within Tx message and reported in remote Rx completion.
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*/
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u32 immediate_data;
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u16 ah;
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u16 reserved;
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/* Queue key */
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u32 qkey;
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u8 reserved2[12];
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};
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/*
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* Tx queue buffer descriptor, for any transport type. Preceded by metadata
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* descriptor.
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*/
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struct efa_io_tx_buf_desc {
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/* length in bytes */
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u32 length;
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/*
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* 23:0 : lkey - local memory translation key
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* 31:24 : reserved - MBZ
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*/
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u32 lkey;
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/* Buffer address bits[31:0] */
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u32 buf_addr_lo;
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/* Buffer address bits[63:32] */
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u32 buf_addr_hi;
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};
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struct efa_io_remote_mem_addr {
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/* length in bytes */
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u32 length;
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/* remote memory translation key */
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u32 rkey;
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/* Buffer address bits[31:0] */
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u32 buf_addr_lo;
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/* Buffer address bits[63:32] */
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u32 buf_addr_hi;
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};
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struct efa_io_rdma_req {
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/* Remote memory address */
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struct efa_io_remote_mem_addr remote_mem;
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/* Local memory address */
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struct efa_io_tx_buf_desc local_mem[1];
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};
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/*
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* Tx WQE, composed of tx meta descriptors followed by either tx buffer
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* descriptors or inline data
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*/
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struct efa_io_tx_wqe {
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/* TX meta */
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struct efa_io_tx_meta_desc meta;
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union {
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/* Send buffer descriptors */
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struct efa_io_tx_buf_desc sgl[2];
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u8 inline_data[32];
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/* RDMA local and remote memory addresses */
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struct efa_io_rdma_req rdma_req;
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} data;
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};
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/*
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* Rx buffer descriptor; RX WQE is composed of one or more RX buffer
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* descriptors.
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*/
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struct efa_io_rx_desc {
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/* Buffer address bits[31:0] */
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u32 buf_addr_lo;
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/* Buffer Pointer[63:32] */
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u32 buf_addr_hi;
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/* Verbs-generated request id. */
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u16 req_id;
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/* Length in bytes. */
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u16 length;
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/*
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* LKey and control flags
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* 23:0 : lkey
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* 29:24 : reserved - MBZ
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* 30 : first - Indicates first descriptor in WQE
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* 31 : last - Indicates last descriptor in WQE
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*/
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u32 lkey_ctrl;
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};
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/* Common IO completion descriptor */
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struct efa_io_cdesc_common {
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/*
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* verbs-generated request ID, as provided in the completed tx or rx
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* descriptor.
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*/
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u16 req_id;
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u8 status;
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/*
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* flags
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* 0 : phase - Phase bit
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* 2:1 : q_type - enum efa_io_queue_type: send/recv
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* 3 : has_imm - indicates that immediate data is
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* present - for RX completions only
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* 6:4 : op_type - enum efa_io_send_op_type
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* 7 : reserved31 - MBZ
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*/
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u8 flags;
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/* local QP number */
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u16 qp_num;
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};
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/* Tx completion descriptor */
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struct efa_io_tx_cdesc {
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/* Common completion info */
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struct efa_io_cdesc_common common;
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/* MBZ */
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u16 reserved16;
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};
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/* Rx Completion Descriptor */
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struct efa_io_rx_cdesc {
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/* Common completion info */
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struct efa_io_cdesc_common common;
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/* Transferred length bits[15:0] */
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u16 length;
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/* Remote Address Handle FW index, 0xFFFF indicates invalid ah */
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u16 ah;
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u16 src_qp_num;
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/* Immediate data */
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u32 imm;
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};
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/* Rx Completion Descriptor RDMA write info */
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struct efa_io_rx_cdesc_rdma_write {
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/* Transferred length bits[31:16] */
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u16 length_hi;
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};
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/* Extended Rx Completion Descriptor */
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struct efa_io_rx_cdesc_ex {
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/* Base RX completion info */
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struct efa_io_rx_cdesc base;
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union {
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struct efa_io_rx_cdesc_rdma_write rdma_write;
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/*
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* Valid only in case of unknown AH (0xFFFF) and CQ
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* set_src_addr is enabled.
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*/
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u8 src_addr[16];
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} u;
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};
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/* tx_meta_desc */
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#define EFA_IO_TX_META_DESC_OP_TYPE_MASK GENMASK(3, 0)
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#define EFA_IO_TX_META_DESC_HAS_IMM_MASK BIT(4)
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#define EFA_IO_TX_META_DESC_INLINE_MSG_MASK BIT(5)
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#define EFA_IO_TX_META_DESC_META_EXTENSION_MASK BIT(6)
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#define EFA_IO_TX_META_DESC_META_DESC_MASK BIT(7)
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#define EFA_IO_TX_META_DESC_PHASE_MASK BIT(0)
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#define EFA_IO_TX_META_DESC_FIRST_MASK BIT(2)
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#define EFA_IO_TX_META_DESC_LAST_MASK BIT(3)
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#define EFA_IO_TX_META_DESC_COMP_REQ_MASK BIT(4)
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/* tx_buf_desc */
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#define EFA_IO_TX_BUF_DESC_LKEY_MASK GENMASK(23, 0)
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/* rx_desc */
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#define EFA_IO_RX_DESC_LKEY_MASK GENMASK(23, 0)
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#define EFA_IO_RX_DESC_FIRST_MASK BIT(30)
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#define EFA_IO_RX_DESC_LAST_MASK BIT(31)
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/* cdesc_common */
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#define EFA_IO_CDESC_COMMON_PHASE_MASK BIT(0)
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#define EFA_IO_CDESC_COMMON_Q_TYPE_MASK GENMASK(2, 1)
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#define EFA_IO_CDESC_COMMON_HAS_IMM_MASK BIT(3)
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#define EFA_IO_CDESC_COMMON_OP_TYPE_MASK GENMASK(6, 4)
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#endif /* _EFA_IO_H_ */
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