305 lines
8.6 KiB
C
305 lines
8.6 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
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/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved.
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*
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* Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
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*/
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#ifndef __AMD_ACP_H
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#define __AMD_ACP_H
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#include <sound/pcm.h>
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#include <sound/soc.h>
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#include <sound/soc-acpi.h>
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#include <sound/soc-dai.h>
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#include "chip_offset_byte.h"
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#define ACP3X_DEV 3
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#define ACP6X_DEV 6
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#define DMIC_INSTANCE 0x00
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#define I2S_SP_INSTANCE 0x01
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#define I2S_BT_INSTANCE 0x02
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#define I2S_HS_INSTANCE 0x03
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#define MEM_WINDOW_START 0x4080000
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#define ACP_I2S_REG_START 0x1242400
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#define ACP_I2S_REG_END 0x1242810
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#define ACP3x_I2STDM_REG_START 0x1242400
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#define ACP3x_I2STDM_REG_END 0x1242410
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#define ACP3x_BT_TDM_REG_START 0x1242800
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#define ACP3x_BT_TDM_REG_END 0x1242810
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#define THRESHOLD(bit, base) ((bit) + (base))
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#define I2S_RX_THRESHOLD(base) THRESHOLD(7, base)
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#define I2S_TX_THRESHOLD(base) THRESHOLD(8, base)
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#define BT_TX_THRESHOLD(base) THRESHOLD(6, base)
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#define BT_RX_THRESHOLD(base) THRESHOLD(5, base)
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#define HS_TX_THRESHOLD(base) THRESHOLD(4, base)
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#define HS_RX_THRESHOLD(base) THRESHOLD(3, base)
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#define ACP_SRAM_SP_PB_PTE_OFFSET 0x0
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#define ACP_SRAM_SP_CP_PTE_OFFSET 0x100
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#define ACP_SRAM_BT_PB_PTE_OFFSET 0x200
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#define ACP_SRAM_BT_CP_PTE_OFFSET 0x300
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#define ACP_SRAM_PDM_PTE_OFFSET 0x400
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#define ACP_SRAM_HS_PB_PTE_OFFSET 0x500
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#define ACP_SRAM_HS_CP_PTE_OFFSET 0x600
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#define PAGE_SIZE_4K_ENABLE 0x2
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#define I2S_SP_TX_MEM_WINDOW_START 0x4000000
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#define I2S_SP_RX_MEM_WINDOW_START 0x4020000
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#define I2S_BT_TX_MEM_WINDOW_START 0x4040000
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#define I2S_BT_RX_MEM_WINDOW_START 0x4060000
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#define I2S_HS_TX_MEM_WINDOW_START 0x40A0000
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#define I2S_HS_RX_MEM_WINDOW_START 0x40C0000
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#define SP_PB_FIFO_ADDR_OFFSET 0x500
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#define SP_CAPT_FIFO_ADDR_OFFSET 0x700
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#define BT_PB_FIFO_ADDR_OFFSET 0x900
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#define BT_CAPT_FIFO_ADDR_OFFSET 0xB00
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#define HS_PB_FIFO_ADDR_OFFSET 0xD00
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#define HS_CAPT_FIFO_ADDR_OFFSET 0xF00
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#define PLAYBACK_MIN_NUM_PERIODS 2
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#define PLAYBACK_MAX_NUM_PERIODS 8
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#define PLAYBACK_MAX_PERIOD_SIZE 8192
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#define PLAYBACK_MIN_PERIOD_SIZE 1024
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#define CAPTURE_MIN_NUM_PERIODS 2
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#define CAPTURE_MAX_NUM_PERIODS 8
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#define CAPTURE_MAX_PERIOD_SIZE 8192
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#define CAPTURE_MIN_PERIOD_SIZE 1024
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#define MAX_BUFFER 65536
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#define MIN_BUFFER MAX_BUFFER
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#define FIFO_SIZE 0x100
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#define DMA_SIZE 0x40
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#define FRM_LEN 0x100
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#define ACP3x_ITER_IRER_SAMP_LEN_MASK 0x38
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#define ACP_MAX_STREAM 8
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#define TDM_ENABLE 1
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#define TDM_DISABLE 0
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#define SLOT_WIDTH_8 0x8
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#define SLOT_WIDTH_16 0x10
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#define SLOT_WIDTH_24 0x18
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#define SLOT_WIDTH_32 0x20
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#define ACP6X_PGFSM_CONTROL 0x1024
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#define ACP6X_PGFSM_STATUS 0x1028
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#define ACP_SOFT_RST_DONE_MASK 0x00010001
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#define ACP_PGFSM_CNTL_POWER_ON_MASK 0x01
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#define ACP_PGFSM_CNTL_POWER_OFF_MASK 0x00
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#define ACP_PGFSM_STATUS_MASK 0x03
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#define ACP_POWERED_ON 0x00
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#define ACP_POWER_ON_IN_PROGRESS 0x01
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#define ACP_POWERED_OFF 0x02
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#define ACP_POWER_OFF_IN_PROGRESS 0x03
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#define ACP_ERROR_MASK 0x20000000
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#define ACP_EXT_INTR_STAT_CLEAR_MASK 0xffffffff
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#define ACP_TIMEOUT 500
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#define DELAY_US 5
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#define ACP_SUSPEND_DELAY_MS 2000
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#define PDM_DMA_STAT 0x10
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#define PDM_DMA_INTR_MASK 0x10000
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#define PDM_DEC_64 0x2
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#define PDM_CLK_FREQ_MASK 0x07
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#define PDM_MISC_CTRL_MASK 0x10
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#define PDM_ENABLE 0x01
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#define PDM_DISABLE 0x00
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#define DMA_EN_MASK 0x02
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#define DELAY_US 5
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#define PDM_TIMEOUT 1000
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#define ACP_REGION2_OFFSET 0x02000000
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struct acp_chip_info {
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char *name; /* Platform name */
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unsigned int acp_rev; /* ACP Revision id */
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void __iomem *base; /* ACP memory PCI base */
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struct platform_device *chip_pdev;
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};
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struct acp_stream {
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struct list_head list;
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struct snd_pcm_substream *substream;
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int irq_bit;
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int dai_id;
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int id;
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int dir;
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u64 bytescount;
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u32 reg_offset;
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u32 pte_offset;
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u32 fifo_offset;
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};
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struct acp_resource {
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int offset;
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int no_of_ctrls;
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int irqp_used;
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bool soc_mclk;
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u32 irq_reg_offset;
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u32 i2s_pin_cfg_offset;
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int i2s_mode;
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u64 scratch_reg_offset;
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u64 sram_pte_offset;
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};
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struct acp_dev_data {
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char *name;
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struct device *dev;
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void __iomem *acp_base;
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unsigned int i2s_irq;
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bool tdm_mode;
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/* SOC specific dais */
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struct snd_soc_dai_driver *dai_driver;
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int num_dai;
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struct list_head stream_list;
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spinlock_t acp_lock;
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struct snd_soc_acpi_mach *machines;
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struct platform_device *mach_dev;
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u32 bclk_div;
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u32 lrclk_div;
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struct acp_resource *rsrc;
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u32 ch_mask;
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u32 tdm_tx_fmt[3];
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u32 tdm_rx_fmt[3];
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u32 xfer_tx_resolution[3];
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u32 xfer_rx_resolution[3];
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};
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union acp_i2stdm_mstrclkgen {
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struct {
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u32 i2stdm_master_mode : 1;
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u32 i2stdm_format_mode : 1;
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u32 i2stdm_lrclk_div_val : 9;
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u32 i2stdm_bclk_div_val : 11;
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u32:10;
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} bitfields, bits;
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u32 u32_all;
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};
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extern const struct snd_soc_dai_ops asoc_acp_cpu_dai_ops;
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extern const struct snd_soc_dai_ops acp_dmic_dai_ops;
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int asoc_acp_i2s_probe(struct snd_soc_dai *dai);
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int acp_platform_register(struct device *dev);
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int acp_platform_unregister(struct device *dev);
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int acp_machine_select(struct acp_dev_data *adata);
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int smn_read(struct pci_dev *dev, u32 smn_addr);
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int smn_write(struct pci_dev *dev, u32 smn_addr, u32 data);
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int acp_init(struct acp_chip_info *chip);
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int acp_deinit(void __iomem *base);
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void acp_enable_interrupts(struct acp_dev_data *adata);
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void acp_disable_interrupts(struct acp_dev_data *adata);
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/* Machine configuration */
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int snd_amd_acp_find_config(struct pci_dev *pci);
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void config_pte_for_stream(struct acp_dev_data *adata, struct acp_stream *stream);
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void config_acp_dma(struct acp_dev_data *adata, struct acp_stream *stream, int size);
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void restore_acp_pdm_params(struct snd_pcm_substream *substream,
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struct acp_dev_data *adata);
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int restore_acp_i2s_params(struct snd_pcm_substream *substream,
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struct acp_dev_data *adata, struct acp_stream *stream);
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static inline u64 acp_get_byte_count(struct acp_dev_data *adata, int dai_id, int direction)
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{
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u64 byte_count = 0, low = 0, high = 0;
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if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
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switch (dai_id) {
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case I2S_BT_INSTANCE:
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high = readl(adata->acp_base + ACP_BT_TX_LINEARPOSITIONCNTR_HIGH);
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low = readl(adata->acp_base + ACP_BT_TX_LINEARPOSITIONCNTR_LOW);
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break;
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case I2S_SP_INSTANCE:
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high = readl(adata->acp_base + ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH);
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low = readl(adata->acp_base + ACP_I2S_TX_LINEARPOSITIONCNTR_LOW);
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break;
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case I2S_HS_INSTANCE:
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high = readl(adata->acp_base + ACP_HS_TX_LINEARPOSITIONCNTR_HIGH);
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low = readl(adata->acp_base + ACP_HS_TX_LINEARPOSITIONCNTR_LOW);
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break;
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default:
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dev_err(adata->dev, "Invalid dai id %x\n", dai_id);
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goto POINTER_RETURN_BYTES;
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}
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} else {
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switch (dai_id) {
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case I2S_BT_INSTANCE:
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high = readl(adata->acp_base + ACP_BT_RX_LINEARPOSITIONCNTR_HIGH);
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low = readl(adata->acp_base + ACP_BT_RX_LINEARPOSITIONCNTR_LOW);
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break;
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case I2S_SP_INSTANCE:
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high = readl(adata->acp_base + ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH);
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low = readl(adata->acp_base + ACP_I2S_RX_LINEARPOSITIONCNTR_LOW);
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break;
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case I2S_HS_INSTANCE:
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high = readl(adata->acp_base + ACP_HS_RX_LINEARPOSITIONCNTR_HIGH);
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low = readl(adata->acp_base + ACP_HS_RX_LINEARPOSITIONCNTR_LOW);
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break;
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case DMIC_INSTANCE:
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high = readl(adata->acp_base + ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH);
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low = readl(adata->acp_base + ACP_WOV_RX_LINEARPOSITIONCNTR_LOW);
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break;
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default:
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dev_err(adata->dev, "Invalid dai id %x\n", dai_id);
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goto POINTER_RETURN_BYTES;
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}
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}
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/* Get 64 bit value from two 32 bit registers */
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byte_count = (high << 32) | low;
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POINTER_RETURN_BYTES:
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return byte_count;
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}
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static inline void acp_set_i2s_clk(struct acp_dev_data *adata, int dai_id)
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{
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union acp_i2stdm_mstrclkgen mclkgen;
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u32 master_reg;
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switch (dai_id) {
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case I2S_SP_INSTANCE:
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master_reg = ACP_I2STDM0_MSTRCLKGEN;
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break;
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case I2S_BT_INSTANCE:
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master_reg = ACP_I2STDM1_MSTRCLKGEN;
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break;
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case I2S_HS_INSTANCE:
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master_reg = ACP_I2STDM2_MSTRCLKGEN;
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break;
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default:
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master_reg = ACP_I2STDM0_MSTRCLKGEN;
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break;
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}
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mclkgen.bits.i2stdm_master_mode = 0x1;
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mclkgen.bits.i2stdm_format_mode = 0x00;
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mclkgen.bits.i2stdm_bclk_div_val = adata->bclk_div;
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mclkgen.bits.i2stdm_lrclk_div_val = adata->lrclk_div;
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writel(mclkgen.u32_all, adata->acp_base + master_reg);
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}
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#endif
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