221 lines
7.0 KiB
C
221 lines
7.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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// Copyright (c) 2024 Hisilicon Limited.
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#include <linux/io.h>
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#include <linux/delay.h>
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#include "dp_config.h"
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#include "dp_comm.h"
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#include "dp_reg.h"
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#include "dp_hw.h"
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static void hibmc_dp_set_tu(struct hibmc_dp_dev *dp, struct drm_display_mode *mode)
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{
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u32 tu_symbol_frac_size;
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u32 tu_symbol_size;
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u32 rate_ks;
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u8 lane_num;
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u32 value;
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u32 bpp;
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lane_num = dp->link.cap.lanes;
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if (lane_num == 0) {
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drm_err(dp->dev, "set tu failed, lane num cannot be 0!\n");
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return;
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}
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bpp = HIBMC_DP_BPP;
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rate_ks = dp->link.cap.link_rate * HIBMC_DP_LINK_RATE_CAL;
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value = (mode->clock * bpp * 5) / (61 * lane_num * rate_ks);
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if (value % 10 == 9) { /* 9 carry */
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tu_symbol_size = value / 10 + 1;
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tu_symbol_frac_size = 0;
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} else {
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tu_symbol_size = value / 10;
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tu_symbol_frac_size = value % 10 + 1;
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}
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drm_dbg_dp(dp->dev, "tu value: %u.%u value: %u\n",
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tu_symbol_size, tu_symbol_frac_size, value);
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hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_PACKET,
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HIBMC_DP_CFG_STREAM_TU_SYMBOL_SIZE, tu_symbol_size);
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hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_PACKET,
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HIBMC_DP_CFG_STREAM_TU_SYMBOL_FRAC_SIZE, tu_symbol_frac_size);
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}
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static void hibmc_dp_set_sst(struct hibmc_dp_dev *dp, struct drm_display_mode *mode)
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{
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u32 hblank_size;
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u32 htotal_size;
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u32 htotal_int;
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u32 hblank_int;
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u32 fclk; /* flink_clock */
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fclk = dp->link.cap.link_rate * HIBMC_DP_LINK_RATE_CAL;
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/* Considering the effect of spread spectrum, the value may be deviated.
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* The coefficient (0.9947) is used to offset the deviation.
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*/
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htotal_int = mode->htotal * 9947 / 10000;
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htotal_size = htotal_int * fclk / (HIBMC_DP_SYMBOL_PER_FCLK * (mode->clock / 1000));
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hblank_int = mode->htotal - mode->hdisplay - mode->hdisplay * 53 / 10000;
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hblank_size = hblank_int * fclk * 9947 /
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(mode->clock * 10 * HIBMC_DP_SYMBOL_PER_FCLK);
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drm_dbg_dp(dp->dev, "h_active %u v_active %u htotal_size %u hblank_size %u",
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mode->hdisplay, mode->vdisplay, htotal_size, hblank_size);
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drm_dbg_dp(dp->dev, "flink_clock %u pixel_clock %d", fclk, mode->clock / 1000);
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hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_HORIZONTAL_SIZE,
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HIBMC_DP_CFG_STREAM_HTOTAL_SIZE, htotal_size);
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hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_HORIZONTAL_SIZE,
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HIBMC_DP_CFG_STREAM_HBLANK_SIZE, hblank_size);
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}
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static void hibmc_dp_link_cfg(struct hibmc_dp_dev *dp, struct drm_display_mode *mode)
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{
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u32 timing_delay;
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u32 vblank;
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u32 hstart;
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u32 vstart;
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vblank = mode->vtotal - mode->vdisplay;
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timing_delay = mode->htotal - mode->hsync_start;
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hstart = mode->htotal - mode->hsync_start;
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vstart = mode->vtotal - mode->vsync_start;
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hibmc_dp_reg_write_field(dp, HIBMC_DP_TIMING_GEN_CONFIG0,
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HIBMC_DP_CFG_TIMING_GEN0_HBLANK, mode->htotal - mode->hdisplay);
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hibmc_dp_reg_write_field(dp, HIBMC_DP_TIMING_GEN_CONFIG0,
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HIBMC_DP_CFG_TIMING_GEN0_HACTIVE, mode->hdisplay);
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hibmc_dp_reg_write_field(dp, HIBMC_DP_TIMING_GEN_CONFIG2,
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HIBMC_DP_CFG_TIMING_GEN0_VBLANK, vblank);
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hibmc_dp_reg_write_field(dp, HIBMC_DP_TIMING_GEN_CONFIG2,
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HIBMC_DP_CFG_TIMING_GEN0_VACTIVE, mode->vdisplay);
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hibmc_dp_reg_write_field(dp, HIBMC_DP_TIMING_GEN_CONFIG3,
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HIBMC_DP_CFG_TIMING_GEN0_VFRONT_PORCH,
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mode->vsync_start - mode->vdisplay);
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hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_CONFIG0,
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HIBMC_DP_CFG_STREAM_HACTIVE, mode->hdisplay);
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hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_CONFIG0,
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HIBMC_DP_CFG_STREAM_HBLANK, mode->htotal - mode->hdisplay);
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hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_CONFIG2,
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HIBMC_DP_CFG_STREAM_HSYNC_WIDTH,
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mode->hsync_end - mode->hsync_start);
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hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_CONFIG1,
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HIBMC_DP_CFG_STREAM_VACTIVE, mode->vdisplay);
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hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_CONFIG1,
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HIBMC_DP_CFG_STREAM_VBLANK, vblank);
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hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_CONFIG3,
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HIBMC_DP_CFG_STREAM_VFRONT_PORCH,
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mode->vsync_start - mode->vdisplay);
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hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_CONFIG3,
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HIBMC_DP_CFG_STREAM_VSYNC_WIDTH,
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mode->vsync_end - mode->vsync_start);
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hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_MSA0,
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HIBMC_DP_CFG_STREAM_VSTART, vstart);
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hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_MSA0,
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HIBMC_DP_CFG_STREAM_HSTART, hstart);
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hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_CTRL, HIBMC_DP_CFG_STREAM_VSYNC_POLARITY,
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mode->flags & DRM_MODE_FLAG_PVSYNC ? 1 : 0);
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hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_CTRL, HIBMC_DP_CFG_STREAM_HSYNC_POLARITY,
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mode->flags & DRM_MODE_FLAG_PHSYNC ? 1 : 0);
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/* MSA mic 0 and 1 */
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writel(HIBMC_DP_MSA1, dp->base + HIBMC_DP_VIDEO_MSA1);
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writel(HIBMC_DP_MSA2, dp->base + HIBMC_DP_VIDEO_MSA2);
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hibmc_dp_set_tu(dp, mode);
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hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_CTRL, HIBMC_DP_CFG_STREAM_RGB_ENABLE, 0x1);
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hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_CTRL, HIBMC_DP_CFG_STREAM_VIDEO_MAPPING, 0);
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/* divide 2: up even */
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if (timing_delay % 2)
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timing_delay++;
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hibmc_dp_reg_write_field(dp, HIBMC_DP_TIMING_MODEL_CTRL,
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HIBMC_DP_CFG_PIXEL_NUM_TIMING_MODE_SEL1, timing_delay);
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hibmc_dp_set_sst(dp, mode);
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}
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int hibmc_dp_hw_init(struct hibmc_dp *dp)
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{
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struct drm_device *drm_dev = dp->drm_dev;
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struct hibmc_dp_dev *dp_dev;
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dp_dev = devm_kzalloc(drm_dev->dev, sizeof(struct hibmc_dp_dev), GFP_KERNEL);
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if (!dp_dev)
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return -ENOMEM;
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mutex_init(&dp_dev->lock);
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dp->dp_dev = dp_dev;
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dp_dev->dev = drm_dev;
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dp_dev->base = dp->mmio + HIBMC_DP_OFFSET;
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hibmc_dp_aux_init(dp_dev);
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dp_dev->link.cap.lanes = 0x2;
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dp_dev->link.cap.link_rate = DP_LINK_BW_2_7;
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/* hdcp data */
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writel(HIBMC_DP_HDCP, dp_dev->base + HIBMC_DP_HDCP_CFG);
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/* int init */
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writel(0, dp_dev->base + HIBMC_DP_INTR_ENABLE);
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writel(HIBMC_DP_INT_RST, dp_dev->base + HIBMC_DP_INTR_ORIGINAL_STATUS);
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/* rst */
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writel(HIBMC_DP_DPTX_RST, dp_dev->base + HIBMC_DP_DPTX_RST_CTRL);
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/* clock enable */
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writel(HIBMC_DP_CLK_EN, dp_dev->base + HIBMC_DP_DPTX_CLK_CTRL);
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return 0;
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}
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void hibmc_dp_display_en(struct hibmc_dp *dp, bool enable)
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{
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struct hibmc_dp_dev *dp_dev = dp->dp_dev;
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if (enable) {
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hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_VIDEO_CTRL, BIT(0), 0x1);
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writel(HIBMC_DP_SYNC_EN_MASK, dp_dev->base + HIBMC_DP_TIMING_SYNC_CTRL);
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hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_DPTX_GCTL0, BIT(10), 0x1);
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writel(HIBMC_DP_SYNC_EN_MASK, dp_dev->base + HIBMC_DP_TIMING_SYNC_CTRL);
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} else {
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hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_DPTX_GCTL0, BIT(10), 0);
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writel(HIBMC_DP_SYNC_EN_MASK, dp_dev->base + HIBMC_DP_TIMING_SYNC_CTRL);
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hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_VIDEO_CTRL, BIT(0), 0);
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writel(HIBMC_DP_SYNC_EN_MASK, dp_dev->base + HIBMC_DP_TIMING_SYNC_CTRL);
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}
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msleep(50);
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}
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int hibmc_dp_mode_set(struct hibmc_dp *dp, struct drm_display_mode *mode)
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{
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struct hibmc_dp_dev *dp_dev = dp->dp_dev;
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int ret;
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if (!dp_dev->link.status.channel_equalized) {
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ret = hibmc_dp_link_training(dp_dev);
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if (ret) {
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drm_err(dp->drm_dev, "dp link training failed, ret: %d\n", ret);
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return ret;
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}
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}
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hibmc_dp_display_en(dp, false);
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hibmc_dp_link_cfg(dp_dev, mode);
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return 0;
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}
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