792 lines
23 KiB
C
792 lines
23 KiB
C
// SPDX-License-Identifier: GPL-2.0 OR MIT
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/*
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* Copyright 2014-2024 Advanced Micro Devices, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "amdgpu.h"
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#include "amdgpu_jpeg.h"
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#include "amdgpu_pm.h"
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#include "soc15.h"
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#include "soc15d.h"
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#include "jpeg_v4_0_3.h"
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#include "jpeg_v5_0_1.h"
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#include "vcn/vcn_5_0_0_offset.h"
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#include "vcn/vcn_5_0_0_sh_mask.h"
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#include "ivsrcid/vcn/irqsrcs_vcn_5_0.h"
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static void jpeg_v5_0_1_set_dec_ring_funcs(struct amdgpu_device *adev);
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static void jpeg_v5_0_1_set_irq_funcs(struct amdgpu_device *adev);
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static int jpeg_v5_0_1_set_powergating_state(struct amdgpu_ip_block *ip_block,
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enum amd_powergating_state state);
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static void jpeg_v5_0_1_dec_ring_set_wptr(struct amdgpu_ring *ring);
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static int amdgpu_ih_srcid_jpeg[] = {
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VCN_5_0__SRCID__JPEG_DECODE,
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VCN_5_0__SRCID__JPEG1_DECODE,
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VCN_5_0__SRCID__JPEG2_DECODE,
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VCN_5_0__SRCID__JPEG3_DECODE,
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VCN_5_0__SRCID__JPEG4_DECODE,
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VCN_5_0__SRCID__JPEG5_DECODE,
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VCN_5_0__SRCID__JPEG6_DECODE,
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VCN_5_0__SRCID__JPEG7_DECODE,
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VCN_5_0__SRCID__JPEG8_DECODE,
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VCN_5_0__SRCID__JPEG9_DECODE,
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};
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static const struct amdgpu_hwip_reg_entry jpeg_reg_list_5_0_1[] = {
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SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS),
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SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT),
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SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_RPTR),
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SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_WPTR),
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SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_STATUS),
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SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE),
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SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG),
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SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_Y_GFX10_TILING_SURFACE),
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SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_UV_GFX10_TILING_SURFACE),
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SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH),
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SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_UV_PITCH),
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SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_RB_RPTR),
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SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_RB_WPTR),
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SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_STATUS),
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SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_RB_RPTR),
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SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_RB_WPTR),
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SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_STATUS),
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SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_RB_RPTR),
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SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_RB_WPTR),
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SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_STATUS),
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SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_RB_RPTR),
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SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_RB_WPTR),
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SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_STATUS),
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SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_RB_RPTR),
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SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_RB_WPTR),
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SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_STATUS),
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SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_RB_RPTR),
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SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_RB_WPTR),
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SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_STATUS),
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SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_RB_RPTR),
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SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_RB_WPTR),
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SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_STATUS),
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SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC8_UVD_JRBC_RB_RPTR),
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SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC8_UVD_JRBC_RB_WPTR),
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SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC8_UVD_JRBC_STATUS),
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SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC9_UVD_JRBC_RB_RPTR),
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SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC9_UVD_JRBC_RB_WPTR),
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SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC9_UVD_JRBC_STATUS),
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};
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static int jpeg_v5_0_1_core_reg_offset(u32 pipe)
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{
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if (pipe <= AMDGPU_MAX_JPEG_RINGS_4_0_3)
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return ((0x40 * pipe) - 0xc80);
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else
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return ((0x40 * pipe) - 0x440);
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}
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/**
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* jpeg_v5_0_1_early_init - set function pointers
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*
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* @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
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*
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* Set ring and irq function pointers
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*/
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static int jpeg_v5_0_1_early_init(struct amdgpu_ip_block *ip_block)
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{
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struct amdgpu_device *adev = ip_block->adev;
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if (!adev->jpeg.num_jpeg_inst || adev->jpeg.num_jpeg_inst > AMDGPU_MAX_JPEG_INSTANCES)
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return -ENOENT;
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adev->jpeg.num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS;
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jpeg_v5_0_1_set_dec_ring_funcs(adev);
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jpeg_v5_0_1_set_irq_funcs(adev);
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return 0;
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}
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/**
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* jpeg_v5_0_1_sw_init - sw init for JPEG block
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*
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* @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
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*
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* Load firmware and sw initialization
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*/
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static int jpeg_v5_0_1_sw_init(struct amdgpu_ip_block *ip_block)
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{
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struct amdgpu_device *adev = ip_block->adev;
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struct amdgpu_ring *ring;
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int i, j, r, jpeg_inst;
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for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
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/* JPEG TRAP */
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r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
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amdgpu_ih_srcid_jpeg[j], &adev->jpeg.inst->irq);
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if (r)
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return r;
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}
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r = amdgpu_jpeg_sw_init(adev);
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if (r)
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return r;
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r = amdgpu_jpeg_resume(adev);
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if (r)
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return r;
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for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
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jpeg_inst = GET_INST(JPEG, i);
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for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
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ring = &adev->jpeg.inst[i].ring_dec[j];
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ring->use_doorbell = false;
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ring->vm_hub = AMDGPU_MMHUB0(adev->jpeg.inst[i].aid_id);
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if (!amdgpu_sriov_vf(adev)) {
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ring->doorbell_index =
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(adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
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1 + j + 11 * jpeg_inst;
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} else {
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if (j < 4)
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ring->doorbell_index =
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(adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
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4 + j + 32 * jpeg_inst;
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else
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ring->doorbell_index =
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(adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
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8 + j + 32 * jpeg_inst;
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}
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sprintf(ring->name, "jpeg_dec_%d.%d", adev->jpeg.inst[i].aid_id, j);
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r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,
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AMDGPU_RING_PRIO_DEFAULT, NULL);
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if (r)
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return r;
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adev->jpeg.internal.jpeg_pitch[j] =
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regUVD_JRBC0_UVD_JRBC_SCRATCH0_INTERNAL_OFFSET;
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adev->jpeg.inst[i].external.jpeg_pitch[j] =
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SOC15_REG_OFFSET1(JPEG, jpeg_inst, regUVD_JRBC_SCRATCH0,
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(j ? jpeg_v5_0_1_core_reg_offset(j) : 0));
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}
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}
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r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_5_0_1, ARRAY_SIZE(jpeg_reg_list_5_0_1));
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if (r)
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return r;
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if (!amdgpu_sriov_vf(adev)) {
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adev->jpeg.supported_reset = AMDGPU_RESET_TYPE_PER_QUEUE;
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r = amdgpu_jpeg_sysfs_reset_mask_init(adev);
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if (r)
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return r;
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}
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return 0;
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}
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/**
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* jpeg_v5_0_1_sw_fini - sw fini for JPEG block
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*
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* @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
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*
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* JPEG suspend and free up sw allocation
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*/
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static int jpeg_v5_0_1_sw_fini(struct amdgpu_ip_block *ip_block)
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{
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struct amdgpu_device *adev = ip_block->adev;
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int r;
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r = amdgpu_jpeg_suspend(adev);
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if (r)
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return r;
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if (!amdgpu_sriov_vf(adev))
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amdgpu_jpeg_sysfs_reset_mask_fini(adev);
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r = amdgpu_jpeg_sw_fini(adev);
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return r;
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}
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/**
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* jpeg_v5_0_1_hw_init - start and test JPEG block
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*
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* @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
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*
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*/
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static int jpeg_v5_0_1_hw_init(struct amdgpu_ip_block *ip_block)
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{
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struct amdgpu_device *adev = ip_block->adev;
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struct amdgpu_ring *ring;
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int i, j, r, jpeg_inst;
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if (amdgpu_sriov_vf(adev)) {
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/* jpeg_v5_0_1_start_sriov(adev); */
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for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
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for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
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ring = &adev->jpeg.inst[i].ring_dec[j];
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ring->wptr = 0;
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ring->wptr_old = 0;
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jpeg_v5_0_1_dec_ring_set_wptr(ring);
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ring->sched.ready = true;
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}
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}
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return 0;
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}
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if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 0x100)
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adev->jpeg.caps |= AMDGPU_JPEG_CAPS(RRMT_ENABLED);
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for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
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jpeg_inst = GET_INST(JPEG, i);
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ring = adev->jpeg.inst[i].ring_dec;
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if (ring->use_doorbell)
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adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
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(adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 11 * jpeg_inst,
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adev->jpeg.inst[i].aid_id);
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for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
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ring = &adev->jpeg.inst[i].ring_dec[j];
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if (ring->use_doorbell)
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WREG32_SOC15_OFFSET(VCN, GET_INST(VCN, i), regVCN_JPEG_DB_CTRL,
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(ring->pipe ? (ring->pipe - 0x15) : 0),
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ring->doorbell_index <<
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VCN_JPEG_DB_CTRL__OFFSET__SHIFT |
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VCN_JPEG_DB_CTRL__EN_MASK);
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r = amdgpu_ring_test_helper(ring);
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if (r)
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return r;
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}
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}
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return 0;
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}
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/**
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* jpeg_v5_0_1_hw_fini - stop the hardware block
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*
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* @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
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*
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* Stop the JPEG block, mark ring as not ready any more
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*/
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static int jpeg_v5_0_1_hw_fini(struct amdgpu_ip_block *ip_block)
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{
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struct amdgpu_device *adev = ip_block->adev;
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int ret = 0;
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cancel_delayed_work_sync(&adev->jpeg.idle_work);
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if (adev->jpeg.cur_state != AMD_PG_STATE_GATE)
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ret = jpeg_v5_0_1_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
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return ret;
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}
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/**
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* jpeg_v5_0_1_suspend - suspend JPEG block
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*
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* @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
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*
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* HW fini and suspend JPEG block
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*/
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static int jpeg_v5_0_1_suspend(struct amdgpu_ip_block *ip_block)
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{
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struct amdgpu_device *adev = ip_block->adev;
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int r;
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r = jpeg_v5_0_1_hw_fini(ip_block);
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if (r)
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return r;
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r = amdgpu_jpeg_suspend(adev);
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return r;
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}
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/**
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* jpeg_v5_0_1_resume - resume JPEG block
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*
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* @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
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*
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* Resume firmware and hw init JPEG block
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*/
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static int jpeg_v5_0_1_resume(struct amdgpu_ip_block *ip_block)
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{
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struct amdgpu_device *adev = ip_block->adev;
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int r;
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r = amdgpu_jpeg_resume(adev);
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if (r)
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return r;
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r = jpeg_v5_0_1_hw_init(ip_block);
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return r;
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}
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static void jpeg_v5_0_1_init_inst(struct amdgpu_device *adev, int i)
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{
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int jpeg_inst = GET_INST(JPEG, i);
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/* disable anti hang mechanism */
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WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS), 0,
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~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
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/* keep the JPEG in static PG mode */
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WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS), 0,
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~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK);
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/* MJPEG global tiling registers */
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WREG32_SOC15(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG,
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adev->gfx.config.gb_addr_config);
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/* enable JMI channel */
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WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 0,
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~UVD_JMI_CNTL__SOFT_RESET_MASK);
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}
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static void jpeg_v5_0_1_deinit_inst(struct amdgpu_device *adev, int i)
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{
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int jpeg_inst = GET_INST(JPEG, i);
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/* reset JMI */
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WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL),
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UVD_JMI_CNTL__SOFT_RESET_MASK,
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~UVD_JMI_CNTL__SOFT_RESET_MASK);
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/* enable anti hang mechanism */
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WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS),
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UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,
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~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
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}
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static void jpeg_v5_0_1_init_jrbc(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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u32 reg, data, mask;
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int jpeg_inst = GET_INST(JPEG, ring->me);
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int reg_offset = ring->pipe ? jpeg_v5_0_1_core_reg_offset(ring->pipe) : 0;
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/* enable System Interrupt for JRBC */
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reg = SOC15_REG_OFFSET(JPEG, jpeg_inst, regJPEG_SYS_INT_EN);
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if (ring->pipe < AMDGPU_MAX_JPEG_RINGS_4_0_3) {
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data = JPEG_SYS_INT_EN__DJRBC0_MASK << ring->pipe;
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mask = ~(JPEG_SYS_INT_EN__DJRBC0_MASK << ring->pipe);
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WREG32_P(reg, data, mask);
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} else {
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data = JPEG_SYS_INT_EN__DJRBC0_MASK << (ring->pipe+12);
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mask = ~(JPEG_SYS_INT_EN__DJRBC0_MASK << (ring->pipe+12));
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WREG32_P(reg, data, mask);
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}
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WREG32_SOC15_OFFSET(JPEG, jpeg_inst,
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regUVD_LMI_JRBC_RB_VMID,
|
|
reg_offset, 0);
|
|
WREG32_SOC15_OFFSET(JPEG, jpeg_inst,
|
|
regUVD_JRBC_RB_CNTL,
|
|
reg_offset,
|
|
(0x00000001L | 0x00000002L));
|
|
WREG32_SOC15_OFFSET(JPEG, jpeg_inst,
|
|
regUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
|
|
reg_offset, lower_32_bits(ring->gpu_addr));
|
|
WREG32_SOC15_OFFSET(JPEG, jpeg_inst,
|
|
regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
|
|
reg_offset, upper_32_bits(ring->gpu_addr));
|
|
WREG32_SOC15_OFFSET(JPEG, jpeg_inst,
|
|
regUVD_JRBC_RB_RPTR,
|
|
reg_offset, 0);
|
|
WREG32_SOC15_OFFSET(JPEG, jpeg_inst,
|
|
regUVD_JRBC_RB_WPTR,
|
|
reg_offset, 0);
|
|
WREG32_SOC15_OFFSET(JPEG, jpeg_inst,
|
|
regUVD_JRBC_RB_CNTL,
|
|
reg_offset, 0x00000002L);
|
|
WREG32_SOC15_OFFSET(JPEG, jpeg_inst,
|
|
regUVD_JRBC_RB_SIZE,
|
|
reg_offset, ring->ring_size / 4);
|
|
ring->wptr = RREG32_SOC15_OFFSET(JPEG, jpeg_inst, regUVD_JRBC_RB_WPTR,
|
|
reg_offset);
|
|
}
|
|
|
|
/**
|
|
* jpeg_v5_0_1_start - start JPEG block
|
|
*
|
|
* @adev: amdgpu_device pointer
|
|
*
|
|
* Setup and start the JPEG block
|
|
*/
|
|
static int jpeg_v5_0_1_start(struct amdgpu_device *adev)
|
|
{
|
|
struct amdgpu_ring *ring;
|
|
int i, j;
|
|
|
|
for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
|
|
jpeg_v5_0_1_init_inst(adev, i);
|
|
for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
|
|
ring = &adev->jpeg.inst[i].ring_dec[j];
|
|
jpeg_v5_0_1_init_jrbc(ring);
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* jpeg_v5_0_1_stop - stop JPEG block
|
|
*
|
|
* @adev: amdgpu_device pointer
|
|
*
|
|
* stop the JPEG block
|
|
*/
|
|
static int jpeg_v5_0_1_stop(struct amdgpu_device *adev)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i)
|
|
jpeg_v5_0_1_deinit_inst(adev, i);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* jpeg_v5_0_1_dec_ring_get_rptr - get read pointer
|
|
*
|
|
* @ring: amdgpu_ring pointer
|
|
*
|
|
* Returns the current hardware read pointer
|
|
*/
|
|
static uint64_t jpeg_v5_0_1_dec_ring_get_rptr(struct amdgpu_ring *ring)
|
|
{
|
|
struct amdgpu_device *adev = ring->adev;
|
|
|
|
return RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC_RB_RPTR,
|
|
ring->pipe ? jpeg_v5_0_1_core_reg_offset(ring->pipe) : 0);
|
|
}
|
|
|
|
/**
|
|
* jpeg_v5_0_1_dec_ring_get_wptr - get write pointer
|
|
*
|
|
* @ring: amdgpu_ring pointer
|
|
*
|
|
* Returns the current hardware write pointer
|
|
*/
|
|
static uint64_t jpeg_v5_0_1_dec_ring_get_wptr(struct amdgpu_ring *ring)
|
|
{
|
|
struct amdgpu_device *adev = ring->adev;
|
|
|
|
if (ring->use_doorbell)
|
|
return adev->wb.wb[ring->wptr_offs];
|
|
|
|
return RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC_RB_WPTR,
|
|
ring->pipe ? jpeg_v5_0_1_core_reg_offset(ring->pipe) : 0);
|
|
}
|
|
|
|
/**
|
|
* jpeg_v5_0_1_dec_ring_set_wptr - set write pointer
|
|
*
|
|
* @ring: amdgpu_ring pointer
|
|
*
|
|
* Commits the write pointer to the hardware
|
|
*/
|
|
static void jpeg_v5_0_1_dec_ring_set_wptr(struct amdgpu_ring *ring)
|
|
{
|
|
struct amdgpu_device *adev = ring->adev;
|
|
|
|
if (ring->use_doorbell) {
|
|
adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
|
|
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
|
|
} else {
|
|
WREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me),
|
|
regUVD_JRBC_RB_WPTR,
|
|
(ring->pipe ? jpeg_v5_0_1_core_reg_offset(ring->pipe) : 0),
|
|
lower_32_bits(ring->wptr));
|
|
}
|
|
}
|
|
|
|
static bool jpeg_v5_0_1_is_idle(struct amdgpu_ip_block *ip_block)
|
|
{
|
|
struct amdgpu_device *adev = ip_block->adev;
|
|
bool ret = false;
|
|
int i, j;
|
|
|
|
for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
|
|
for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
|
|
int reg_offset = (j ? jpeg_v5_0_1_core_reg_offset(j) : 0);
|
|
|
|
ret &= ((RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, i),
|
|
regUVD_JRBC_STATUS, reg_offset) &
|
|
UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
|
|
UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int jpeg_v5_0_1_wait_for_idle(struct amdgpu_ip_block *ip_block)
|
|
{
|
|
struct amdgpu_device *adev = ip_block->adev;
|
|
int ret = 0;
|
|
int i, j;
|
|
|
|
for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
|
|
for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
|
|
int reg_offset = (j ? jpeg_v5_0_1_core_reg_offset(j) : 0);
|
|
|
|
ret &= SOC15_WAIT_ON_RREG_OFFSET(JPEG, GET_INST(JPEG, i),
|
|
regUVD_JRBC_STATUS, reg_offset,
|
|
UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
|
|
UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
|
|
}
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static int jpeg_v5_0_1_set_clockgating_state(struct amdgpu_ip_block *ip_block,
|
|
enum amd_clockgating_state state)
|
|
{
|
|
struct amdgpu_device *adev = ip_block->adev;
|
|
bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
|
|
|
|
int i;
|
|
|
|
if (!enable)
|
|
return 0;
|
|
|
|
for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
|
|
if (!jpeg_v5_0_1_is_idle(ip_block))
|
|
return -EBUSY;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int jpeg_v5_0_1_set_powergating_state(struct amdgpu_ip_block *ip_block,
|
|
enum amd_powergating_state state)
|
|
{
|
|
struct amdgpu_device *adev = ip_block->adev;
|
|
int ret;
|
|
|
|
if (state == adev->jpeg.cur_state)
|
|
return 0;
|
|
|
|
if (state == AMD_PG_STATE_GATE)
|
|
ret = jpeg_v5_0_1_stop(adev);
|
|
else
|
|
ret = jpeg_v5_0_1_start(adev);
|
|
|
|
if (!ret)
|
|
adev->jpeg.cur_state = state;
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int jpeg_v5_0_1_set_interrupt_state(struct amdgpu_device *adev,
|
|
struct amdgpu_irq_src *source,
|
|
unsigned int type,
|
|
enum amdgpu_interrupt_state state)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int jpeg_v5_0_1_process_interrupt(struct amdgpu_device *adev,
|
|
struct amdgpu_irq_src *source,
|
|
struct amdgpu_iv_entry *entry)
|
|
{
|
|
u32 i, inst;
|
|
|
|
i = node_id_to_phys_map[entry->node_id];
|
|
DRM_DEV_DEBUG(adev->dev, "IH: JPEG TRAP\n");
|
|
|
|
for (inst = 0; inst < adev->jpeg.num_jpeg_inst; ++inst)
|
|
if (adev->jpeg.inst[inst].aid_id == i)
|
|
break;
|
|
|
|
if (inst >= adev->jpeg.num_jpeg_inst) {
|
|
dev_WARN_ONCE(adev->dev, 1,
|
|
"Interrupt received for unknown JPEG instance %d",
|
|
entry->node_id);
|
|
return 0;
|
|
}
|
|
|
|
switch (entry->src_id) {
|
|
case VCN_5_0__SRCID__JPEG_DECODE:
|
|
amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[0]);
|
|
break;
|
|
case VCN_5_0__SRCID__JPEG1_DECODE:
|
|
amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[1]);
|
|
break;
|
|
case VCN_5_0__SRCID__JPEG2_DECODE:
|
|
amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[2]);
|
|
break;
|
|
case VCN_5_0__SRCID__JPEG3_DECODE:
|
|
amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[3]);
|
|
break;
|
|
case VCN_5_0__SRCID__JPEG4_DECODE:
|
|
amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[4]);
|
|
break;
|
|
case VCN_5_0__SRCID__JPEG5_DECODE:
|
|
amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[5]);
|
|
break;
|
|
case VCN_5_0__SRCID__JPEG6_DECODE:
|
|
amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[6]);
|
|
break;
|
|
case VCN_5_0__SRCID__JPEG7_DECODE:
|
|
amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[7]);
|
|
break;
|
|
case VCN_5_0__SRCID__JPEG8_DECODE:
|
|
amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[8]);
|
|
break;
|
|
case VCN_5_0__SRCID__JPEG9_DECODE:
|
|
amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[9]);
|
|
break;
|
|
default:
|
|
DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n",
|
|
entry->src_id, entry->src_data[0]);
|
|
break;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void jpeg_v5_0_1_core_stall_reset(struct amdgpu_ring *ring)
|
|
{
|
|
struct amdgpu_device *adev = ring->adev;
|
|
int jpeg_inst = GET_INST(JPEG, ring->me);
|
|
int reg_offset = ring->pipe ? jpeg_v5_0_1_core_reg_offset(ring->pipe) : 0;
|
|
|
|
WREG32_SOC15_OFFSET(JPEG, jpeg_inst,
|
|
regUVD_JMI0_UVD_JMI_CLIENT_STALL,
|
|
reg_offset, 0x1F);
|
|
SOC15_WAIT_ON_RREG_OFFSET(JPEG, jpeg_inst,
|
|
regUVD_JMI0_UVD_JMI_CLIENT_CLEAN_STATUS,
|
|
reg_offset, 0x1F, 0x1F);
|
|
WREG32_SOC15_OFFSET(JPEG, jpeg_inst,
|
|
regUVD_JMI0_JPEG_LMI_DROP,
|
|
reg_offset, 0x1F);
|
|
WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CORE_RST_CTRL, 1 << ring->pipe);
|
|
WREG32_SOC15_OFFSET(JPEG, jpeg_inst,
|
|
regUVD_JMI0_UVD_JMI_CLIENT_STALL,
|
|
reg_offset, 0x00);
|
|
WREG32_SOC15_OFFSET(JPEG, jpeg_inst,
|
|
regUVD_JMI0_JPEG_LMI_DROP,
|
|
reg_offset, 0x00);
|
|
WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CORE_RST_CTRL, 0x00);
|
|
}
|
|
|
|
static int jpeg_v5_0_1_ring_reset(struct amdgpu_ring *ring, unsigned int vmid)
|
|
{
|
|
if (amdgpu_sriov_vf(ring->adev))
|
|
return -EOPNOTSUPP;
|
|
|
|
jpeg_v5_0_1_core_stall_reset(ring);
|
|
jpeg_v5_0_1_init_jrbc(ring);
|
|
return amdgpu_ring_test_helper(ring);
|
|
}
|
|
|
|
static const struct amd_ip_funcs jpeg_v5_0_1_ip_funcs = {
|
|
.name = "jpeg_v5_0_1",
|
|
.early_init = jpeg_v5_0_1_early_init,
|
|
.late_init = NULL,
|
|
.sw_init = jpeg_v5_0_1_sw_init,
|
|
.sw_fini = jpeg_v5_0_1_sw_fini,
|
|
.hw_init = jpeg_v5_0_1_hw_init,
|
|
.hw_fini = jpeg_v5_0_1_hw_fini,
|
|
.suspend = jpeg_v5_0_1_suspend,
|
|
.resume = jpeg_v5_0_1_resume,
|
|
.is_idle = jpeg_v5_0_1_is_idle,
|
|
.wait_for_idle = jpeg_v5_0_1_wait_for_idle,
|
|
.check_soft_reset = NULL,
|
|
.pre_soft_reset = NULL,
|
|
.soft_reset = NULL,
|
|
.post_soft_reset = NULL,
|
|
.set_clockgating_state = jpeg_v5_0_1_set_clockgating_state,
|
|
.set_powergating_state = jpeg_v5_0_1_set_powergating_state,
|
|
.dump_ip_state = amdgpu_jpeg_dump_ip_state,
|
|
.print_ip_state = amdgpu_jpeg_print_ip_state,
|
|
};
|
|
|
|
static const struct amdgpu_ring_funcs jpeg_v5_0_1_dec_ring_vm_funcs = {
|
|
.type = AMDGPU_RING_TYPE_VCN_JPEG,
|
|
.align_mask = 0xf,
|
|
.get_rptr = jpeg_v5_0_1_dec_ring_get_rptr,
|
|
.get_wptr = jpeg_v5_0_1_dec_ring_get_wptr,
|
|
.set_wptr = jpeg_v5_0_1_dec_ring_set_wptr,
|
|
.emit_frame_size =
|
|
SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
|
|
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
|
|
8 + /* jpeg_v5_0_1_dec_ring_emit_vm_flush */
|
|
22 + 22 + /* jpeg_v5_0_1_dec_ring_emit_fence x2 vm fence */
|
|
8 + 16,
|
|
.emit_ib_size = 22, /* jpeg_v5_0_1_dec_ring_emit_ib */
|
|
.emit_ib = jpeg_v4_0_3_dec_ring_emit_ib,
|
|
.emit_fence = jpeg_v4_0_3_dec_ring_emit_fence,
|
|
.emit_vm_flush = jpeg_v4_0_3_dec_ring_emit_vm_flush,
|
|
.emit_hdp_flush = jpeg_v4_0_3_ring_emit_hdp_flush,
|
|
.test_ring = amdgpu_jpeg_dec_ring_test_ring,
|
|
.test_ib = amdgpu_jpeg_dec_ring_test_ib,
|
|
.insert_nop = jpeg_v4_0_3_dec_ring_nop,
|
|
.insert_start = jpeg_v4_0_3_dec_ring_insert_start,
|
|
.insert_end = jpeg_v4_0_3_dec_ring_insert_end,
|
|
.pad_ib = amdgpu_ring_generic_pad_ib,
|
|
.begin_use = amdgpu_jpeg_ring_begin_use,
|
|
.end_use = amdgpu_jpeg_ring_end_use,
|
|
.emit_wreg = jpeg_v4_0_3_dec_ring_emit_wreg,
|
|
.emit_reg_wait = jpeg_v4_0_3_dec_ring_emit_reg_wait,
|
|
.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
|
|
.reset = jpeg_v5_0_1_ring_reset,
|
|
};
|
|
|
|
static void jpeg_v5_0_1_set_dec_ring_funcs(struct amdgpu_device *adev)
|
|
{
|
|
int i, j, jpeg_inst;
|
|
|
|
for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
|
|
for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
|
|
adev->jpeg.inst[i].ring_dec[j].funcs = &jpeg_v5_0_1_dec_ring_vm_funcs;
|
|
adev->jpeg.inst[i].ring_dec[j].me = i;
|
|
adev->jpeg.inst[i].ring_dec[j].pipe = j;
|
|
}
|
|
jpeg_inst = GET_INST(JPEG, i);
|
|
adev->jpeg.inst[i].aid_id =
|
|
jpeg_inst / adev->jpeg.num_inst_per_aid;
|
|
}
|
|
}
|
|
|
|
static const struct amdgpu_irq_src_funcs jpeg_v5_0_1_irq_funcs = {
|
|
.set = jpeg_v5_0_1_set_interrupt_state,
|
|
.process = jpeg_v5_0_1_process_interrupt,
|
|
};
|
|
|
|
static void jpeg_v5_0_1_set_irq_funcs(struct amdgpu_device *adev)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i)
|
|
adev->jpeg.inst->irq.num_types += adev->jpeg.num_jpeg_rings;
|
|
|
|
adev->jpeg.inst->irq.funcs = &jpeg_v5_0_1_irq_funcs;
|
|
}
|
|
|
|
const struct amdgpu_ip_block_version jpeg_v5_0_1_ip_block = {
|
|
.type = AMD_IP_BLOCK_TYPE_JPEG,
|
|
.major = 5,
|
|
.minor = 0,
|
|
.rev = 1,
|
|
.funcs = &jpeg_v5_0_1_ip_funcs,
|
|
};
|