412 lines
12 KiB
C
412 lines
12 KiB
C
// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
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/*
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* Copyright (c) 2024-2025, NVIDIA CORPORATION & AFFILIATES
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*/
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#include <linux/fwctl.h>
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#include <linux/auxiliary_bus.h>
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#include <linux/mlx5/device.h>
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#include <linux/mlx5/driver.h>
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#include <uapi/fwctl/mlx5.h>
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#define mlx5ctl_err(mcdev, format, ...) \
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dev_err(&mcdev->fwctl.dev, format, ##__VA_ARGS__)
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#define mlx5ctl_dbg(mcdev, format, ...) \
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dev_dbg(&mcdev->fwctl.dev, "PID %u: " format, current->pid, \
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##__VA_ARGS__)
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struct mlx5ctl_uctx {
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struct fwctl_uctx uctx;
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u32 uctx_caps;
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u32 uctx_uid;
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};
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struct mlx5ctl_dev {
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struct fwctl_device fwctl;
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struct mlx5_core_dev *mdev;
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};
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DEFINE_FREE(mlx5ctl, struct mlx5ctl_dev *, if (_T) fwctl_put(&_T->fwctl));
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struct mlx5_ifc_mbox_in_hdr_bits {
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u8 opcode[0x10];
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u8 uid[0x10];
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u8 reserved_at_20[0x10];
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u8 op_mod[0x10];
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u8 reserved_at_40[0x40];
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};
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struct mlx5_ifc_mbox_out_hdr_bits {
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u8 status[0x8];
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u8 reserved_at_8[0x18];
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u8 syndrome[0x20];
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u8 reserved_at_40[0x40];
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};
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enum {
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MLX5_UCTX_OBJECT_CAP_TOOLS_RESOURCES = 0x4,
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};
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enum {
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MLX5_CMD_OP_QUERY_DRIVER_VERSION = 0x10c,
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MLX5_CMD_OP_QUERY_OTHER_HCA_CAP = 0x10e,
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MLX5_CMD_OP_QUERY_RDB = 0x512,
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MLX5_CMD_OP_QUERY_PSV = 0x602,
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MLX5_CMD_OP_QUERY_DC_CNAK_TRACE = 0x716,
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MLX5_CMD_OP_QUERY_NVMF_BACKEND_CONTROLLER = 0x722,
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MLX5_CMD_OP_QUERY_NVMF_NAMESPACE_CONTEXT = 0x728,
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MLX5_CMD_OP_QUERY_BURST_SIZE = 0x813,
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MLX5_CMD_OP_QUERY_DIAGNOSTIC_PARAMS = 0x819,
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MLX5_CMD_OP_SET_DIAGNOSTIC_PARAMS = 0x820,
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MLX5_CMD_OP_QUERY_DIAGNOSTIC_COUNTERS = 0x821,
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MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS = 0x911,
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MLX5_CMD_OP_QUERY_AFU = 0x971,
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MLX5_CMD_OP_QUERY_CAPI_PEC = 0x981,
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MLX5_CMD_OP_QUERY_UCTX = 0xa05,
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MLX5_CMD_OP_QUERY_UMEM = 0xa09,
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MLX5_CMD_OP_QUERY_NVMF_CC_RESPONSE = 0xb02,
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MLX5_CMD_OP_QUERY_EMULATED_FUNCTIONS_INFO = 0xb03,
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MLX5_CMD_OP_QUERY_REGEXP_PARAMS = 0xb05,
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MLX5_CMD_OP_QUERY_REGEXP_REGISTER = 0xb07,
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MLX5_CMD_OP_USER_QUERY_XRQ_DC_PARAMS_ENTRY = 0xb08,
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MLX5_CMD_OP_USER_QUERY_XRQ_ERROR_PARAMS = 0xb0a,
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MLX5_CMD_OP_ACCESS_REGISTER_USER = 0xb0c,
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MLX5_CMD_OP_QUERY_EMULATION_DEVICE_EQ_MSIX_MAPPING = 0xb0f,
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MLX5_CMD_OP_QUERY_MATCH_SAMPLE_INFO = 0xb13,
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MLX5_CMD_OP_QUERY_CRYPTO_STATE = 0xb14,
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MLX5_CMD_OP_QUERY_VUID = 0xb22,
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MLX5_CMD_OP_QUERY_DPA_PARTITION = 0xb28,
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MLX5_CMD_OP_QUERY_DPA_PARTITIONS = 0xb2a,
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MLX5_CMD_OP_POSTPONE_CONNECTED_QP_TIMEOUT = 0xb2e,
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MLX5_CMD_OP_QUERY_EMULATED_RESOURCES_INFO = 0xb2f,
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MLX5_CMD_OP_QUERY_RSV_RESOURCES = 0x8000,
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MLX5_CMD_OP_QUERY_MTT = 0x8001,
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MLX5_CMD_OP_QUERY_SCHED_QUEUE = 0x8006,
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};
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static int mlx5ctl_alloc_uid(struct mlx5ctl_dev *mcdev, u32 cap)
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{
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u32 out[MLX5_ST_SZ_DW(create_uctx_out)] = {};
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u32 in[MLX5_ST_SZ_DW(create_uctx_in)] = {};
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void *uctx;
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int ret;
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u16 uid;
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uctx = MLX5_ADDR_OF(create_uctx_in, in, uctx);
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mlx5ctl_dbg(mcdev, "%s: caps 0x%x\n", __func__, cap);
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MLX5_SET(create_uctx_in, in, opcode, MLX5_CMD_OP_CREATE_UCTX);
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MLX5_SET(uctx, uctx, cap, cap);
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ret = mlx5_cmd_exec(mcdev->mdev, in, sizeof(in), out, sizeof(out));
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if (ret)
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return ret;
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uid = MLX5_GET(create_uctx_out, out, uid);
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mlx5ctl_dbg(mcdev, "allocated uid %u with caps 0x%x\n", uid, cap);
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return uid;
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}
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static void mlx5ctl_release_uid(struct mlx5ctl_dev *mcdev, u16 uid)
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{
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u32 in[MLX5_ST_SZ_DW(destroy_uctx_in)] = {};
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struct mlx5_core_dev *mdev = mcdev->mdev;
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int ret;
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MLX5_SET(destroy_uctx_in, in, opcode, MLX5_CMD_OP_DESTROY_UCTX);
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MLX5_SET(destroy_uctx_in, in, uid, uid);
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ret = mlx5_cmd_exec_in(mdev, destroy_uctx, in);
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mlx5ctl_dbg(mcdev, "released uid %u %pe\n", uid, ERR_PTR(ret));
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}
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static int mlx5ctl_open_uctx(struct fwctl_uctx *uctx)
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{
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struct mlx5ctl_uctx *mfd =
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container_of(uctx, struct mlx5ctl_uctx, uctx);
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struct mlx5ctl_dev *mcdev =
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container_of(uctx->fwctl, struct mlx5ctl_dev, fwctl);
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int uid;
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/*
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* New FW supports the TOOLS_RESOURCES uid security label
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* which allows commands to manipulate the global device state.
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* Otherwise only basic existing RDMA devx privilege are allowed.
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*/
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if (MLX5_CAP_GEN(mcdev->mdev, uctx_cap) &
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MLX5_UCTX_OBJECT_CAP_TOOLS_RESOURCES)
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mfd->uctx_caps |= MLX5_UCTX_OBJECT_CAP_TOOLS_RESOURCES;
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uid = mlx5ctl_alloc_uid(mcdev, mfd->uctx_caps);
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if (uid < 0)
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return uid;
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mfd->uctx_uid = uid;
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return 0;
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}
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static void mlx5ctl_close_uctx(struct fwctl_uctx *uctx)
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{
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struct mlx5ctl_dev *mcdev =
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container_of(uctx->fwctl, struct mlx5ctl_dev, fwctl);
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struct mlx5ctl_uctx *mfd =
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container_of(uctx, struct mlx5ctl_uctx, uctx);
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mlx5ctl_release_uid(mcdev, mfd->uctx_uid);
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}
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static void *mlx5ctl_info(struct fwctl_uctx *uctx, size_t *length)
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{
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struct mlx5ctl_uctx *mfd =
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container_of(uctx, struct mlx5ctl_uctx, uctx);
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struct fwctl_info_mlx5 *info;
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info = kzalloc(sizeof(*info), GFP_KERNEL);
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if (!info)
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return ERR_PTR(-ENOMEM);
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info->uid = mfd->uctx_uid;
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info->uctx_caps = mfd->uctx_caps;
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*length = sizeof(*info);
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return info;
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}
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static bool mlx5ctl_validate_rpc(const void *in, enum fwctl_rpc_scope scope)
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{
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u16 opcode = MLX5_GET(mbox_in_hdr, in, opcode);
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u16 op_mod = MLX5_GET(mbox_in_hdr, in, op_mod);
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/*
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* Currently the driver can't keep track of commands that allocate
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* objects in the FW, these commands are safe from a security
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* perspective but nothing will free the memory when the FD is closed.
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* For now permit only query commands and set commands that don't alter
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* objects. Also the caps for the scope have not been defined yet,
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* filter commands manually for now.
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*/
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switch (opcode) {
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case MLX5_CMD_OP_POSTPONE_CONNECTED_QP_TIMEOUT:
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case MLX5_CMD_OP_QUERY_ADAPTER:
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case MLX5_CMD_OP_QUERY_ESW_FUNCTIONS:
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case MLX5_CMD_OP_QUERY_HCA_CAP:
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case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
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case MLX5_CMD_OP_QUERY_OTHER_HCA_CAP:
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case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
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case MLX5_CMD_OPCODE_QUERY_VUID:
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/*
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* FW limits SET_HCA_CAP on the tools UID to only the other function
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* mode which is used for function pre-configuration
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*/
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case MLX5_CMD_OP_SET_HCA_CAP:
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return true; /* scope >= FWCTL_RPC_CONFIGURATION; */
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case MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS:
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case MLX5_CMD_OP_FPGA_QUERY_QP:
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case MLX5_CMD_OP_NOP:
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case MLX5_CMD_OP_QUERY_AFU:
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case MLX5_CMD_OP_QUERY_BURST_SIZE:
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case MLX5_CMD_OP_QUERY_CAPI_PEC:
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case MLX5_CMD_OP_QUERY_CONG_PARAMS:
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case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
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case MLX5_CMD_OP_QUERY_CONG_STATUS:
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case MLX5_CMD_OP_QUERY_CQ:
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case MLX5_CMD_OP_QUERY_CRYPTO_STATE:
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case MLX5_CMD_OP_QUERY_DC_CNAK_TRACE:
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case MLX5_CMD_OP_QUERY_DCT:
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case MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS:
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case MLX5_CMD_OP_QUERY_DIAGNOSTIC_COUNTERS:
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case MLX5_CMD_OP_QUERY_DIAGNOSTIC_PARAMS:
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case MLX5_CMD_OP_QUERY_DPA_PARTITION:
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case MLX5_CMD_OP_QUERY_DPA_PARTITIONS:
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case MLX5_CMD_OP_QUERY_DRIVER_VERSION:
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case MLX5_CMD_OP_QUERY_EMULATED_FUNCTIONS_INFO:
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case MLX5_CMD_OP_QUERY_EMULATED_RESOURCES_INFO:
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case MLX5_CMD_OP_QUERY_EMULATION_DEVICE_EQ_MSIX_MAPPING:
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case MLX5_CMD_OP_QUERY_EQ:
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case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
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case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
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case MLX5_CMD_OP_QUERY_FLOW_GROUP:
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case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
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case MLX5_CMD_OP_QUERY_FLOW_TABLE:
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case MLX5_CMD_OP_QUERY_GENERAL_OBJECT:
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case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
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case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
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case MLX5_CMD_OP_QUERY_ISSI:
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case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
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case MLX5_CMD_OP_QUERY_LAG:
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case MLX5_CMD_OP_QUERY_MAD_DEMUX:
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case MLX5_CMD_OP_QUERY_MATCH_SAMPLE_INFO:
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case MLX5_CMD_OP_QUERY_MKEY:
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case MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT:
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case MLX5_CMD_OP_QUERY_MTT:
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case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
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case MLX5_CMD_OP_QUERY_NVMF_BACKEND_CONTROLLER:
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case MLX5_CMD_OP_QUERY_NVMF_CC_RESPONSE:
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case MLX5_CMD_OP_QUERY_NVMF_NAMESPACE_CONTEXT:
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case MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT:
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case MLX5_CMD_OP_QUERY_PAGES:
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case MLX5_CMD_OP_QUERY_PSV:
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case MLX5_CMD_OP_QUERY_Q_COUNTER:
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case MLX5_CMD_OP_QUERY_QP:
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case MLX5_CMD_OP_QUERY_RATE_LIMIT:
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case MLX5_CMD_OP_QUERY_RDB:
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case MLX5_CMD_OP_QUERY_REGEXP_PARAMS:
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case MLX5_CMD_OP_QUERY_REGEXP_REGISTER:
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case MLX5_CMD_OP_QUERY_RMP:
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case MLX5_CMD_OP_QUERY_RQ:
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case MLX5_CMD_OP_QUERY_RQT:
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case MLX5_CMD_OP_QUERY_RSV_RESOURCES:
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case MLX5_CMD_OP_QUERY_SCHED_QUEUE:
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case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT:
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case MLX5_CMD_OP_QUERY_SF_PARTITION:
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case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
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case MLX5_CMD_OP_QUERY_SQ:
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case MLX5_CMD_OP_QUERY_SRQ:
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case MLX5_CMD_OP_QUERY_TIR:
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case MLX5_CMD_OP_QUERY_TIS:
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case MLX5_CMD_OP_QUERY_UCTX:
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case MLX5_CMD_OP_QUERY_UMEM:
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case MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE:
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case MLX5_CMD_OP_QUERY_VHCA_STATE:
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case MLX5_CMD_OP_QUERY_VNIC_ENV:
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case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
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case MLX5_CMD_OP_QUERY_VPORT_STATE:
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case MLX5_CMD_OP_QUERY_WOL_ROL:
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case MLX5_CMD_OP_QUERY_XRC_SRQ:
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case MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY:
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case MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS:
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case MLX5_CMD_OP_QUERY_XRQ:
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case MLX5_CMD_OP_USER_QUERY_XRQ_DC_PARAMS_ENTRY:
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case MLX5_CMD_OP_USER_QUERY_XRQ_ERROR_PARAMS:
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return scope >= FWCTL_RPC_DEBUG_READ_ONLY;
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case MLX5_CMD_OP_SET_DIAGNOSTIC_PARAMS:
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return scope >= FWCTL_RPC_DEBUG_WRITE;
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case MLX5_CMD_OP_ACCESS_REG:
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case MLX5_CMD_OP_ACCESS_REGISTER_USER:
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if (op_mod == 0) /* write */
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return true; /* scope >= FWCTL_RPC_CONFIGURATION; */
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return scope >= FWCTL_RPC_DEBUG_READ_ONLY;
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default:
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return false;
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}
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}
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static void *mlx5ctl_fw_rpc(struct fwctl_uctx *uctx, enum fwctl_rpc_scope scope,
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void *rpc_in, size_t in_len, size_t *out_len)
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{
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struct mlx5ctl_dev *mcdev =
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container_of(uctx->fwctl, struct mlx5ctl_dev, fwctl);
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struct mlx5ctl_uctx *mfd =
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container_of(uctx, struct mlx5ctl_uctx, uctx);
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void *rpc_out;
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int ret;
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if (in_len < MLX5_ST_SZ_BYTES(mbox_in_hdr) ||
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*out_len < MLX5_ST_SZ_BYTES(mbox_out_hdr))
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return ERR_PTR(-EMSGSIZE);
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mlx5ctl_dbg(mcdev, "[UID %d] cmdif: opcode 0x%x inlen %zu outlen %zu\n",
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mfd->uctx_uid, MLX5_GET(mbox_in_hdr, rpc_in, opcode),
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in_len, *out_len);
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if (!mlx5ctl_validate_rpc(rpc_in, scope))
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return ERR_PTR(-EBADMSG);
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/*
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* mlx5_cmd_do() copies the input message to its own buffer before
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* executing it, so we can reuse the allocation for the output.
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*/
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if (*out_len <= in_len) {
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rpc_out = rpc_in;
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} else {
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rpc_out = kvzalloc(*out_len, GFP_KERNEL);
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if (!rpc_out)
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return ERR_PTR(-ENOMEM);
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}
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/* Enforce the user context for the command */
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MLX5_SET(mbox_in_hdr, rpc_in, uid, mfd->uctx_uid);
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ret = mlx5_cmd_do(mcdev->mdev, rpc_in, in_len, rpc_out, *out_len);
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mlx5ctl_dbg(mcdev,
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"[UID %d] cmdif: opcode 0x%x status 0x%x retval %pe\n",
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mfd->uctx_uid, MLX5_GET(mbox_in_hdr, rpc_in, opcode),
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MLX5_GET(mbox_out_hdr, rpc_out, status), ERR_PTR(ret));
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/*
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* -EREMOTEIO means execution succeeded and the out is valid,
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* but an error code was returned inside out. Everything else
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* means the RPC did not make it to the device.
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*/
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if (ret && ret != -EREMOTEIO) {
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if (rpc_out != rpc_in)
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kfree(rpc_out);
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return ERR_PTR(ret);
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}
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return rpc_out;
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}
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static const struct fwctl_ops mlx5ctl_ops = {
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.device_type = FWCTL_DEVICE_TYPE_MLX5,
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.uctx_size = sizeof(struct mlx5ctl_uctx),
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.open_uctx = mlx5ctl_open_uctx,
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.close_uctx = mlx5ctl_close_uctx,
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.info = mlx5ctl_info,
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.fw_rpc = mlx5ctl_fw_rpc,
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};
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static int mlx5ctl_probe(struct auxiliary_device *adev,
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const struct auxiliary_device_id *id)
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{
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struct mlx5_adev *madev = container_of(adev, struct mlx5_adev, adev);
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struct mlx5_core_dev *mdev = madev->mdev;
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struct mlx5ctl_dev *mcdev __free(mlx5ctl) = fwctl_alloc_device(
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&mdev->pdev->dev, &mlx5ctl_ops, struct mlx5ctl_dev, fwctl);
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int ret;
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if (!mcdev)
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return -ENOMEM;
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mcdev->mdev = mdev;
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ret = fwctl_register(&mcdev->fwctl);
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if (ret)
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return ret;
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auxiliary_set_drvdata(adev, no_free_ptr(mcdev));
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return 0;
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}
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static void mlx5ctl_remove(struct auxiliary_device *adev)
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{
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struct mlx5ctl_dev *mcdev = auxiliary_get_drvdata(adev);
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fwctl_unregister(&mcdev->fwctl);
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fwctl_put(&mcdev->fwctl);
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}
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static const struct auxiliary_device_id mlx5ctl_id_table[] = {
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{.name = MLX5_ADEV_NAME ".fwctl",},
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{}
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};
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MODULE_DEVICE_TABLE(auxiliary, mlx5ctl_id_table);
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static struct auxiliary_driver mlx5ctl_driver = {
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.name = "mlx5_fwctl",
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.probe = mlx5ctl_probe,
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.remove = mlx5ctl_remove,
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.id_table = mlx5ctl_id_table,
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};
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module_auxiliary_driver(mlx5ctl_driver);
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|
|
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MODULE_IMPORT_NS(FWCTL);
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MODULE_DESCRIPTION("mlx5 ConnectX fwctl driver");
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MODULE_AUTHOR("Saeed Mahameed <saeedm@nvidia.com>");
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|
MODULE_LICENSE("Dual BSD/GPL");
|