133 lines
		
	
	
		
			4.8 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			133 lines
		
	
	
		
			4.8 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
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| /*
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|  * This file is provided under a dual BSD/GPLv2 license.  When using or
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|  * redistributing this file, you may do so under either license.
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|  *
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|  * Copyright(c) 2018 Intel Corporation
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|  */
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| 
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| #ifndef __INCLUDE_SOUND_SOF_DAI_H__
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| #define __INCLUDE_SOUND_SOF_DAI_H__
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| 
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| #include <sound/sof/header.h>
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| #include <sound/sof/dai-intel.h>
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| #include <sound/sof/dai-imx.h>
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| #include <sound/sof/dai-amd.h>
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| #include <sound/sof/dai-mediatek.h>
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| 
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| /*
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|  * DAI Configuration.
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|  *
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|  * Each different DAI type will have it's own structure and IPC cmd.
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|  */
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| 
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| #define SOF_DAI_FMT_I2S		1 /**< I2S mode */
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| #define SOF_DAI_FMT_RIGHT_J	2 /**< Right Justified mode */
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| #define SOF_DAI_FMT_LEFT_J	3 /**< Left Justified mode */
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| #define SOF_DAI_FMT_DSP_A	4 /**< L data MSB after FRM LRC */
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| #define SOF_DAI_FMT_DSP_B	5 /**< L data MSB during FRM LRC */
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| #define SOF_DAI_FMT_PDM		6 /**< Pulse density modulation */
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| 
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| #define SOF_DAI_FMT_CONT	(1 << 4) /**< continuous clock */
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| #define SOF_DAI_FMT_GATED	(0 << 4) /**< clock is gated */
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| 
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| #define SOF_DAI_FMT_NB_NF	(0 << 8) /**< normal bit clock + frame */
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| #define SOF_DAI_FMT_NB_IF	(2 << 8) /**< normal BCLK + inv FRM */
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| #define SOF_DAI_FMT_IB_NF	(3 << 8) /**< invert BCLK + nor FRM */
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| #define SOF_DAI_FMT_IB_IF	(4 << 8) /**< invert BCLK + FRM */
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| 
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| #define SOF_DAI_FMT_CBP_CFP	(0 << 12) /**< codec bclk provider & frame provider */
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| #define SOF_DAI_FMT_CBC_CFP	(2 << 12) /**< codec bclk consumer & frame provider */
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| #define SOF_DAI_FMT_CBP_CFC	(3 << 12) /**< codec bclk provider & frame consumer */
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| #define SOF_DAI_FMT_CBC_CFC	(4 << 12) /**< codec bclk consumer & frame consumer */
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| 
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| /* keep old definitions for backwards compatibility */
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| #define SOF_DAI_FMT_CBM_CFM	SOF_DAI_FMT_CBP_CFP
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| #define SOF_DAI_FMT_CBS_CFM	SOF_DAI_FMT_CBC_CFP
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| #define SOF_DAI_FMT_CBM_CFS	SOF_DAI_FMT_CBP_CFC
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| #define SOF_DAI_FMT_CBS_CFS	SOF_DAI_FMT_CBC_CFC
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| 
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| #define SOF_DAI_FMT_FORMAT_MASK		0x000f
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| #define SOF_DAI_FMT_CLOCK_MASK		0x00f0
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| #define SOF_DAI_FMT_INV_MASK		0x0f00
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| #define SOF_DAI_FMT_CLOCK_PROVIDER_MASK	0xf000
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| 
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| /*
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|  * DAI_CONFIG flags. The 4 LSB bits are used for the commands, HW_PARAMS, HW_FREE and PAUSE
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|  * representing when the IPC is sent. The 4 MSB bits are used to add quirks along with the above
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|  * commands.
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|  */
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| #define SOF_DAI_CONFIG_FLAGS_CMD_MASK	0xF
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| #define SOF_DAI_CONFIG_FLAGS_NONE	0 /**< DAI_CONFIG sent without stage information */
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| #define SOF_DAI_CONFIG_FLAGS_HW_PARAMS	BIT(0) /**< DAI_CONFIG sent during hw_params stage */
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| #define SOF_DAI_CONFIG_FLAGS_HW_FREE	BIT(1) /**< DAI_CONFIG sent during hw_free stage */
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| /**< DAI_CONFIG sent during pause trigger. Only available ABI 3.20 onwards */
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| #define SOF_DAI_CONFIG_FLAGS_PAUSE	BIT(2)
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| #define SOF_DAI_CONFIG_FLAGS_QUIRK_SHIFT 4
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| #define SOF_DAI_CONFIG_FLAGS_QUIRK_MASK  (0xF << SOF_DAI_CONFIG_FLAGS_QUIRK_SHIFT)
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| /*
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|  * This should be used along with the SOF_DAI_CONFIG_FLAGS_HW_PARAMS to indicate that pipeline
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|  * stop/pause and DAI DMA stop/pause should happen in two steps. This change is only available
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|  * ABI 3.20 onwards.
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|  */
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| #define SOF_DAI_CONFIG_FLAGS_2_STEP_STOP BIT(0)
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| 
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| /** \brief Types of DAI */
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| enum sof_ipc_dai_type {
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| 	SOF_DAI_INTEL_NONE = 0,		/**< None */
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| 	SOF_DAI_INTEL_SSP,		/**< Intel SSP */
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| 	SOF_DAI_INTEL_DMIC,		/**< Intel DMIC */
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| 	SOF_DAI_INTEL_HDA,		/**< Intel HD/A */
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| 	SOF_DAI_INTEL_ALH,		/**< Intel ALH  */
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| 	SOF_DAI_IMX_SAI,		/**< i.MX SAI */
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| 	SOF_DAI_IMX_ESAI,		/**< i.MX ESAI */
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| 	SOF_DAI_AMD_BT,			/**< AMD ACP BT*/
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| 	SOF_DAI_AMD_SP,			/**< AMD ACP SP */
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| 	SOF_DAI_AMD_DMIC,		/**< AMD ACP DMIC */
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| 	SOF_DAI_MEDIATEK_AFE,		/**< Mediatek AFE */
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| 	SOF_DAI_AMD_HS,			/**< Amd HS */
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| 	SOF_DAI_AMD_SP_VIRTUAL,		/**< AMD ACP SP VIRTUAL */
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| 	SOF_DAI_AMD_HS_VIRTUAL,		/**< AMD ACP HS VIRTUAL */
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| 	SOF_DAI_IMX_MICFIL,		/** < i.MX MICFIL PDM */
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| 	SOF_DAI_AMD_SDW,		/**< AMD ACP SDW */
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| };
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| 
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| /* general purpose DAI configuration */
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| struct sof_ipc_dai_config {
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| 	struct sof_ipc_cmd_hdr hdr;
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| 	uint32_t type;		/**< DAI type - enum sof_ipc_dai_type */
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| 	uint32_t dai_index;	/**< index of this type dai */
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| 
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| 	/* physical protocol and clocking */
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| 	uint16_t format;	/**< SOF_DAI_FMT_ */
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| 	uint8_t group_id;	/**< group ID, 0 means no group (ABI 3.17) */
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| 	uint8_t flags;		/**< SOF_DAI_CONFIG_FLAGS_ (ABI 3.19) */
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| 
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| 	/* reserved for future use */
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| 	uint32_t reserved[8];
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| 
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| 	/* HW specific data */
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| 	union {
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| 		struct sof_ipc_dai_ssp_params ssp;
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| 		struct sof_ipc_dai_dmic_params dmic;
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| 		struct sof_ipc_dai_hda_params hda;
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| 		struct sof_ipc_dai_alh_params alh;
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| 		struct sof_ipc_dai_esai_params esai;
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| 		struct sof_ipc_dai_sai_params sai;
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| 		struct sof_ipc_dai_acp_params acpbt;
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| 		struct sof_ipc_dai_acp_params acpsp;
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| 		struct sof_ipc_dai_acpdmic_params acpdmic;
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| 		struct sof_ipc_dai_acp_params acphs;
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| 		struct sof_ipc_dai_mtk_afe_params afe;
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| 		struct sof_ipc_dai_micfil_params micfil;
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| 		struct sof_ipc_dai_acp_sdw_params acp_sdw;
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| 	};
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| } __packed;
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| 
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| struct sof_dai_private_data {
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| 	struct sof_ipc_comp_dai *comp_dai;
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| 	struct sof_ipc_dai_config *dai_config;
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| };
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| 
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| #endif
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