118 lines
3.4 KiB
C
118 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* QMC management
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*
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* Copyright 2022 CS GROUP France
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*
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* Author: Herve Codina <herve.codina@bootlin.com>
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*/
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#ifndef __SOC_FSL_QMC_H__
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#define __SOC_FSL_QMC_H__
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#include <linux/bits.h>
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#include <linux/types.h>
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struct device_node;
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struct device;
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struct qmc_chan;
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int qmc_chan_count_phandles(struct device_node *np, const char *phandles_name);
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struct qmc_chan *qmc_chan_get_byphandles_index(struct device_node *np,
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const char *phandles_name,
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int index);
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struct qmc_chan *devm_qmc_chan_get_byphandles_index(struct device *dev,
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struct device_node *np,
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const char *phandles_name,
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int index);
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static inline struct qmc_chan *qmc_chan_get_byphandle(struct device_node *np,
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const char *phandle_name)
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{
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return qmc_chan_get_byphandles_index(np, phandle_name, 0);
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}
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static inline struct qmc_chan *devm_qmc_chan_get_byphandle(struct device *dev,
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struct device_node *np,
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const char *phandle_name)
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{
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return devm_qmc_chan_get_byphandles_index(dev, np, phandle_name, 0);
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}
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struct qmc_chan *qmc_chan_get_bychild(struct device_node *np);
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void qmc_chan_put(struct qmc_chan *chan);
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struct qmc_chan *devm_qmc_chan_get_bychild(struct device *dev, struct device_node *np);
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enum qmc_mode {
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QMC_TRANSPARENT,
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QMC_HDLC,
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};
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struct qmc_chan_info {
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enum qmc_mode mode;
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unsigned long rx_fs_rate;
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unsigned long rx_bit_rate;
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u8 nb_rx_ts;
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unsigned long tx_fs_rate;
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unsigned long tx_bit_rate;
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u8 nb_tx_ts;
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};
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int qmc_chan_get_info(struct qmc_chan *chan, struct qmc_chan_info *info);
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struct qmc_chan_ts_info {
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u64 rx_ts_mask_avail;
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u64 tx_ts_mask_avail;
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u64 rx_ts_mask;
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u64 tx_ts_mask;
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};
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int qmc_chan_get_ts_info(struct qmc_chan *chan, struct qmc_chan_ts_info *ts_info);
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int qmc_chan_set_ts_info(struct qmc_chan *chan, const struct qmc_chan_ts_info *ts_info);
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struct qmc_chan_param {
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enum qmc_mode mode;
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union {
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struct {
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u16 max_rx_buf_size;
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u16 max_rx_frame_size;
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bool is_crc32;
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} hdlc;
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struct {
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u16 max_rx_buf_size;
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} transp;
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};
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};
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int qmc_chan_set_param(struct qmc_chan *chan, const struct qmc_chan_param *param);
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int qmc_chan_write_submit(struct qmc_chan *chan, dma_addr_t addr, size_t length,
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void (*complete)(void *context), void *context);
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/* Flags available (ORed) for read complete() flags parameter in HDLC mode.
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* No flags are available in transparent mode and the read complete() flags
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* parameter has no meaning in transparent mode.
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*/
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#define QMC_RX_FLAG_HDLC_LAST BIT(11) /* Last in frame */
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#define QMC_RX_FLAG_HDLC_FIRST BIT(10) /* First in frame */
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#define QMC_RX_FLAG_HDLC_OVF BIT(5) /* Data overflow */
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#define QMC_RX_FLAG_HDLC_UNA BIT(4) /* Unaligned (ie. bits received not multiple of 8) */
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#define QMC_RX_FLAG_HDLC_ABORT BIT(3) /* Received an abort sequence (seven consecutive ones) */
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#define QMC_RX_FLAG_HDLC_CRC BIT(2) /* CRC error */
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int qmc_chan_read_submit(struct qmc_chan *chan, dma_addr_t addr, size_t length,
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void (*complete)(void *context, size_t length,
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unsigned int flags),
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void *context);
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#define QMC_CHAN_READ (1<<0)
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#define QMC_CHAN_WRITE (1<<1)
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#define QMC_CHAN_ALL (QMC_CHAN_READ | QMC_CHAN_WRITE)
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int qmc_chan_start(struct qmc_chan *chan, int direction);
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int qmc_chan_stop(struct qmc_chan *chan, int direction);
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int qmc_chan_reset(struct qmc_chan *chan, int direction);
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#endif /* __SOC_FSL_QMC_H__ */
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