88 lines
2.0 KiB
C
88 lines
2.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
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/*
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* Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.
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*/
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#ifndef __DT_BINDINGS_RESET_SOPHGO_SG2042_H_
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#define __DT_BINDINGS_RESET_SOPHGO_SG2042_H_
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#define RST_MAIN_AP 0
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#define RST_RISCV_CPU 1
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#define RST_RISCV_LOW_SPEED_LOGIC 2
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#define RST_RISCV_CMN 3
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#define RST_HSDMA 4
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#define RST_SYSDMA 5
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#define RST_EFUSE0 6
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#define RST_EFUSE1 7
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#define RST_RTC 8
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#define RST_TIMER 9
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#define RST_WDT 10
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#define RST_AHB_ROM0 11
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#define RST_AHB_ROM1 12
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#define RST_I2C0 13
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#define RST_I2C1 14
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#define RST_I2C2 15
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#define RST_I2C3 16
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#define RST_GPIO0 17
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#define RST_GPIO1 18
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#define RST_GPIO2 19
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#define RST_PWM 20
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#define RST_AXI_SRAM0 21
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#define RST_AXI_SRAM1 22
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#define RST_SF0 23
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#define RST_SF1 24
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#define RST_LPC 25
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#define RST_ETH0 26
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#define RST_EMMC 27
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#define RST_SD 28
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#define RST_UART0 29
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#define RST_UART1 30
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#define RST_UART2 31
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#define RST_UART3 32
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#define RST_SPI0 33
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#define RST_SPI1 34
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#define RST_DBG_I2C 35
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#define RST_PCIE0 36
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#define RST_PCIE1 37
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#define RST_DDR0 38
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#define RST_DDR1 39
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#define RST_DDR2 40
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#define RST_DDR3 41
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#define RST_FAU0 42
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#define RST_FAU1 43
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#define RST_FAU2 44
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#define RST_RXU0 45
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#define RST_RXU1 46
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#define RST_RXU2 47
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#define RST_RXU3 48
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#define RST_RXU4 49
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#define RST_RXU5 50
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#define RST_RXU6 51
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#define RST_RXU7 52
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#define RST_RXU8 53
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#define RST_RXU9 54
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#define RST_RXU10 55
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#define RST_RXU11 56
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#define RST_RXU12 57
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#define RST_RXU13 58
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#define RST_RXU14 59
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#define RST_RXU15 60
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#define RST_RXU16 61
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#define RST_RXU17 62
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#define RST_RXU18 63
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#define RST_RXU19 64
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#define RST_RXU20 65
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#define RST_RXU21 66
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#define RST_RXU22 67
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#define RST_RXU23 68
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#define RST_RXU24 69
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#define RST_RXU25 70
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#define RST_RXU26 71
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#define RST_RXU27 72
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#define RST_RXU28 73
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#define RST_RXU29 74
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#define RST_RXU30 75
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#define RST_RXU31 76
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#endif /* __DT_BINDINGS_RESET_SOPHGO_SG2042_H_ */
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