97 lines
2.3 KiB
C
97 lines
2.3 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (C) 2023 Vivo Communication Technology Co. Ltd.
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* Authors: Yangtao Li <frank.li@vivo.com>
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*/
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#ifndef _DT_BINDINGS_CLK_TH1520_H_
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#define _DT_BINDINGS_CLK_TH1520_H_
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#define CLK_CPU_PLL0 0
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#define CLK_CPU_PLL1 1
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#define CLK_GMAC_PLL 2
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#define CLK_VIDEO_PLL 3
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#define CLK_DPU0_PLL 4
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#define CLK_DPU1_PLL 5
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#define CLK_TEE_PLL 6
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#define CLK_C910_I0 7
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#define CLK_C910 8
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#define CLK_BROM 9
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#define CLK_BMU 10
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#define CLK_AHB2_CPUSYS_HCLK 11
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#define CLK_APB3_CPUSYS_PCLK 12
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#define CLK_AXI4_CPUSYS2_ACLK 13
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#define CLK_AON2CPU_A2X 14
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#define CLK_X2X_CPUSYS 15
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#define CLK_AXI_ACLK 16
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#define CLK_CPU2AON_X2H 17
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#define CLK_PERI_AHB_HCLK 18
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#define CLK_CPU2PERI_X2H 19
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#define CLK_PERI_APB_PCLK 20
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#define CLK_PERI2APB_PCLK 21
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#define CLK_PERISYS_APB1_HCLK 22
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#define CLK_PERISYS_APB2_HCLK 23
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#define CLK_PERISYS_APB3_HCLK 24
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#define CLK_PERISYS_APB4_HCLK 25
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#define CLK_OSC12M 26
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#define CLK_OUT1 27
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#define CLK_OUT2 28
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#define CLK_OUT3 29
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#define CLK_OUT4 30
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#define CLK_APB_PCLK 31
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#define CLK_NPU 32
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#define CLK_NPU_AXI 33
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#define CLK_VI 34
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#define CLK_VI_AHB 35
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#define CLK_VO_AXI 36
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#define CLK_VP_APB 37
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#define CLK_VP_AXI 38
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#define CLK_CPU2VP 39
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#define CLK_VENC 40
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#define CLK_DPU0 41
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#define CLK_DPU1 42
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#define CLK_EMMC_SDIO 43
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#define CLK_GMAC1 44
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#define CLK_PADCTRL1 45
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#define CLK_DSMART 46
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#define CLK_PADCTRL0 47
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#define CLK_GMAC_AXI 48
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#define CLK_GPIO3 49
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#define CLK_GMAC0 50
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#define CLK_PWM 51
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#define CLK_QSPI0 52
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#define CLK_QSPI1 53
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#define CLK_SPI 54
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#define CLK_UART0_PCLK 55
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#define CLK_UART1_PCLK 56
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#define CLK_UART2_PCLK 57
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#define CLK_UART3_PCLK 58
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#define CLK_UART4_PCLK 59
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#define CLK_UART5_PCLK 60
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#define CLK_GPIO0 61
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#define CLK_GPIO1 62
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#define CLK_GPIO2 63
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#define CLK_I2C0 64
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#define CLK_I2C1 65
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#define CLK_I2C2 66
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#define CLK_I2C3 67
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#define CLK_I2C4 68
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#define CLK_I2C5 69
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#define CLK_SPINLOCK 70
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#define CLK_DMA 71
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#define CLK_MBOX0 72
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#define CLK_MBOX1 73
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#define CLK_MBOX2 74
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#define CLK_MBOX3 75
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#define CLK_WDT0 76
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#define CLK_WDT1 77
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#define CLK_TIMER0 78
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#define CLK_TIMER1 79
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#define CLK_SRAM0 80
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#define CLK_SRAM1 81
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#define CLK_SRAM2 82
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#define CLK_SRAM3 83
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#define CLK_PLL_GMAC_100M 84
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#define CLK_UART_SCLK 85
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#endif
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