118 lines
		
	
	
		
			2.7 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			118 lines
		
	
	
		
			2.7 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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| /*
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|  * Copyright (C) 2020 Arm Ltd.
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|  */
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| 
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| #ifndef _DT_BINDINGS_CLK_SUN50I_H616_H_
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| #define _DT_BINDINGS_CLK_SUN50I_H616_H_
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| 
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| #define CLK_PLL_PERIPH0		4
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| 
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| #define CLK_CPUX		21
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| 
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| #define CLK_APB1		26
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| 
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| #define CLK_DE			29
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| #define CLK_BUS_DE		30
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| #define CLK_DEINTERLACE		31
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| #define CLK_BUS_DEINTERLACE	32
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| #define CLK_G2D			33
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| #define CLK_BUS_G2D		34
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| #define CLK_GPU0		35
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| #define CLK_BUS_GPU		36
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| #define CLK_GPU1		37
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| #define CLK_CE			38
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| #define CLK_BUS_CE		39
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| #define CLK_VE			40
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| #define CLK_BUS_VE		41
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| #define CLK_BUS_DMA		42
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| #define CLK_BUS_HSTIMER		43
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| #define CLK_AVS			44
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| #define CLK_BUS_DBG		45
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| #define CLK_BUS_PSI		46
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| #define CLK_BUS_PWM		47
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| #define CLK_BUS_IOMMU		48
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| 
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| #define CLK_MBUS_DMA		50
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| #define CLK_MBUS_VE		51
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| #define CLK_MBUS_CE		52
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| #define CLK_MBUS_TS		53
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| #define CLK_MBUS_NAND		54
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| #define CLK_MBUS_G2D		55
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| 
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| #define CLK_NAND0		57
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| #define CLK_NAND1		58
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| #define CLK_BUS_NAND		59
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| #define CLK_MMC0		60
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| #define CLK_MMC1		61
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| #define CLK_MMC2		62
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| #define CLK_BUS_MMC0		63
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| #define CLK_BUS_MMC1		64
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| #define CLK_BUS_MMC2		65
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| #define CLK_BUS_UART0		66
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| #define CLK_BUS_UART1		67
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| #define CLK_BUS_UART2		68
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| #define CLK_BUS_UART3		69
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| #define CLK_BUS_UART4		70
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| #define CLK_BUS_UART5		71
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| #define CLK_BUS_I2C0		72
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| #define CLK_BUS_I2C1		73
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| #define CLK_BUS_I2C2		74
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| #define CLK_BUS_I2C3		75
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| #define CLK_BUS_I2C4		76
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| #define CLK_SPI0		77
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| #define CLK_SPI1		78
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| #define CLK_BUS_SPI0		79
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| #define CLK_BUS_SPI1		80
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| #define CLK_EMAC_25M		81
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| #define CLK_BUS_EMAC0		82
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| #define CLK_BUS_EMAC1		83
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| #define CLK_TS			84
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| #define CLK_BUS_TS		85
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| #define CLK_BUS_THS		86
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| #define CLK_SPDIF		87
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| #define CLK_BUS_SPDIF		88
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| #define CLK_DMIC		89
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| #define CLK_BUS_DMIC		90
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| #define CLK_AUDIO_CODEC_1X	91
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| #define CLK_AUDIO_CODEC_4X	92
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| #define CLK_BUS_AUDIO_CODEC	93
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| #define CLK_AUDIO_HUB		94
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| #define CLK_BUS_AUDIO_HUB	95
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| #define CLK_USB_OHCI0		96
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| #define CLK_USB_PHY0		97
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| #define CLK_USB_OHCI1		98
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| #define CLK_USB_PHY1		99
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| #define CLK_USB_OHCI2		100
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| #define CLK_USB_PHY2		101
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| #define CLK_USB_OHCI3		102
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| #define CLK_USB_PHY3		103
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| #define CLK_BUS_OHCI0		104
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| #define CLK_BUS_OHCI1		105
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| #define CLK_BUS_OHCI2		106
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| #define CLK_BUS_OHCI3		107
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| #define CLK_BUS_EHCI0		108
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| #define CLK_BUS_EHCI1		109
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| #define CLK_BUS_EHCI2		110
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| #define CLK_BUS_EHCI3		111
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| #define CLK_BUS_OTG		112
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| #define CLK_BUS_KEYADC		113
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| #define CLK_HDMI		114
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| #define CLK_HDMI_SLOW		115
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| #define CLK_HDMI_CEC		116
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| #define CLK_BUS_HDMI		117
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| #define CLK_BUS_TCON_TOP	118
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| #define CLK_TCON_TV0		119
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| #define CLK_TCON_TV1		120
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| #define CLK_BUS_TCON_TV0	121
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| #define CLK_BUS_TCON_TV1	122
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| #define CLK_TVE0		123
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| #define CLK_BUS_TVE_TOP		124
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| #define CLK_BUS_TVE0		125
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| #define CLK_HDCP		126
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| #define CLK_BUS_HDCP		127
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| #define CLK_PLL_SYSTEM_32K	128
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| #define CLK_BUS_GPADC		129
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| 
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| #endif /* _DT_BINDINGS_CLK_SUN50I_H616_H_ */
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