112 lines
3.1 KiB
C
112 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
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/*
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* Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.
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*/
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#ifndef __DT_BINDINGS_SOPHGO_SG2042_CLKGEN_H__
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#define __DT_BINDINGS_SOPHGO_SG2042_CLKGEN_H__
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#define DIV_CLK_MPLL_RP_CPU_NORMAL_0 0
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#define DIV_CLK_MPLL_AXI_DDR_0 1
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#define DIV_CLK_FPLL_DDR01_1 2
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#define DIV_CLK_FPLL_DDR23_1 3
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#define DIV_CLK_FPLL_RP_CPU_NORMAL_1 4
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#define DIV_CLK_FPLL_50M_A53 5
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#define DIV_CLK_FPLL_TOP_RP_CMN_DIV2 6
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#define DIV_CLK_FPLL_UART_500M 7
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#define DIV_CLK_FPLL_AHB_LPC 8
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#define DIV_CLK_FPLL_EFUSE 9
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#define DIV_CLK_FPLL_TX_ETH0 10
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#define DIV_CLK_FPLL_PTP_REF_I_ETH0 11
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#define DIV_CLK_FPLL_REF_ETH0 12
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#define DIV_CLK_FPLL_EMMC 13
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#define DIV_CLK_FPLL_SD 14
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#define DIV_CLK_FPLL_TOP_AXI0 15
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#define DIV_CLK_FPLL_TOP_AXI_HSPERI 16
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#define DIV_CLK_FPLL_AXI_DDR_1 17
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#define DIV_CLK_FPLL_DIV_TIMER1 18
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#define DIV_CLK_FPLL_DIV_TIMER2 19
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#define DIV_CLK_FPLL_DIV_TIMER3 20
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#define DIV_CLK_FPLL_DIV_TIMER4 21
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#define DIV_CLK_FPLL_DIV_TIMER5 22
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#define DIV_CLK_FPLL_DIV_TIMER6 23
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#define DIV_CLK_FPLL_DIV_TIMER7 24
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#define DIV_CLK_FPLL_DIV_TIMER8 25
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#define DIV_CLK_FPLL_100K_EMMC 26
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#define DIV_CLK_FPLL_100K_SD 27
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#define DIV_CLK_FPLL_GPIO_DB 28
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#define DIV_CLK_DPLL0_DDR01_0 29
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#define DIV_CLK_DPLL1_DDR23_0 30
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#define GATE_CLK_RP_CPU_NORMAL_DIV0 31
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#define GATE_CLK_AXI_DDR_DIV0 32
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#define GATE_CLK_RP_CPU_NORMAL_DIV1 33
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#define GATE_CLK_A53_50M 34
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#define GATE_CLK_TOP_RP_CMN_DIV2 35
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#define GATE_CLK_HSDMA 36
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#define GATE_CLK_EMMC_100M 37
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#define GATE_CLK_SD_100M 38
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#define GATE_CLK_TX_ETH0 39
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#define GATE_CLK_PTP_REF_I_ETH0 40
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#define GATE_CLK_REF_ETH0 41
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#define GATE_CLK_UART_500M 42
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#define GATE_CLK_EFUSE 43
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#define GATE_CLK_AHB_LPC 44
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#define GATE_CLK_AHB_ROM 45
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#define GATE_CLK_AHB_SF 46
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#define GATE_CLK_APB_UART 47
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#define GATE_CLK_APB_TIMER 48
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#define GATE_CLK_APB_EFUSE 49
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#define GATE_CLK_APB_GPIO 50
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#define GATE_CLK_APB_GPIO_INTR 51
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#define GATE_CLK_APB_SPI 52
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#define GATE_CLK_APB_I2C 53
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#define GATE_CLK_APB_WDT 54
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#define GATE_CLK_APB_PWM 55
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#define GATE_CLK_APB_RTC 56
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#define GATE_CLK_AXI_PCIE0 57
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#define GATE_CLK_AXI_PCIE1 58
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#define GATE_CLK_SYSDMA_AXI 59
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#define GATE_CLK_AXI_DBG_I2C 60
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#define GATE_CLK_AXI_SRAM 61
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#define GATE_CLK_AXI_ETH0 62
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#define GATE_CLK_AXI_EMMC 63
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#define GATE_CLK_AXI_SD 64
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#define GATE_CLK_TOP_AXI0 65
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#define GATE_CLK_TOP_AXI_HSPERI 66
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#define GATE_CLK_TIMER1 67
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#define GATE_CLK_TIMER2 68
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#define GATE_CLK_TIMER3 69
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#define GATE_CLK_TIMER4 70
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#define GATE_CLK_TIMER5 71
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#define GATE_CLK_TIMER6 72
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#define GATE_CLK_TIMER7 73
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#define GATE_CLK_TIMER8 74
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#define GATE_CLK_100K_EMMC 75
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#define GATE_CLK_100K_SD 76
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#define GATE_CLK_GPIO_DB 77
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#define GATE_CLK_AXI_DDR_DIV1 78
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#define GATE_CLK_DDR01_DIV1 79
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#define GATE_CLK_DDR23_DIV1 80
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#define GATE_CLK_DDR01_DIV0 81
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#define GATE_CLK_DDR23_DIV0 82
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#define GATE_CLK_DDR01 83
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#define GATE_CLK_DDR23 84
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#define GATE_CLK_RP_CPU_NORMAL 85
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#define GATE_CLK_AXI_DDR 86
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#define MUX_CLK_DDR01 87
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#define MUX_CLK_DDR23 88
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#define MUX_CLK_RP_CPU_NORMAL 89
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#define MUX_CLK_AXI_DDR 90
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#endif /* __DT_BINDINGS_SOPHGO_SG2042_CLKGEN_H__ */
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