97 lines
2.9 KiB
C
97 lines
2.9 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (C) 2023 Renesas Electronics Corp.
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*/
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#ifndef __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__
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#define __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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/* r8a779h0 CPG Core Clocks */
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#define R8A779H0_CLK_ZX 0
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#define R8A779H0_CLK_ZD 1
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#define R8A779H0_CLK_ZS 2
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#define R8A779H0_CLK_ZT 3
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#define R8A779H0_CLK_ZTR 4
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#define R8A779H0_CLK_S0D2 5
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#define R8A779H0_CLK_S0D3 6
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#define R8A779H0_CLK_S0D4 7
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#define R8A779H0_CLK_S0D1_VIO 8
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#define R8A779H0_CLK_S0D2_VIO 9
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#define R8A779H0_CLK_S0D4_VIO 10
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#define R8A779H0_CLK_S0D8_VIO 11
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#define R8A779H0_CLK_VIOBUSD1 12
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#define R8A779H0_CLK_VIOBUSD2 13
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#define R8A779H0_CLK_S0D1_VC 14
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#define R8A779H0_CLK_S0D2_VC 15
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#define R8A779H0_CLK_S0D4_VC 16
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#define R8A779H0_CLK_VCBUSD1 17
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#define R8A779H0_CLK_VCBUSD2 18
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#define R8A779H0_CLK_S0D2_MM 19
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#define R8A779H0_CLK_S0D4_MM 20
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#define R8A779H0_CLK_S0D2_U3DG 21
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#define R8A779H0_CLK_S0D4_U3DG 22
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#define R8A779H0_CLK_S0D2_RT 23
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#define R8A779H0_CLK_S0D3_RT 24
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#define R8A779H0_CLK_S0D4_RT 25
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#define R8A779H0_CLK_S0D6_RT 26
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#define R8A779H0_CLK_S0D2_PER 27
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#define R8A779H0_CLK_S0D3_PER 28
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#define R8A779H0_CLK_S0D4_PER 29
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#define R8A779H0_CLK_S0D6_PER 30
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#define R8A779H0_CLK_S0D12_PER 31
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#define R8A779H0_CLK_S0D24_PER 32
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#define R8A779H0_CLK_S0D1_HSC 33
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#define R8A779H0_CLK_S0D2_HSC 34
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#define R8A779H0_CLK_S0D4_HSC 35
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#define R8A779H0_CLK_S0D8_HSC 36
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#define R8A779H0_CLK_SVD1_IR 37
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#define R8A779H0_CLK_SVD2_IR 38
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#define R8A779H0_CLK_IMPAD1 39
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#define R8A779H0_CLK_IMPAD4 40
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#define R8A779H0_CLK_IMPB 41
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#define R8A779H0_CLK_SVD1_VIP 42
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#define R8A779H0_CLK_SVD2_VIP 43
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#define R8A779H0_CLK_CL 44
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#define R8A779H0_CLK_CL16M 45
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#define R8A779H0_CLK_CL16M_MM 46
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#define R8A779H0_CLK_CL16M_RT 47
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#define R8A779H0_CLK_CL16M_PER 48
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#define R8A779H0_CLK_CL16M_HSC 49
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#define R8A779H0_CLK_ZC0 50
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#define R8A779H0_CLK_ZC1 51
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#define R8A779H0_CLK_ZC2 52
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#define R8A779H0_CLK_ZC3 53
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#define R8A779H0_CLK_ZB3 54
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#define R8A779H0_CLK_ZB3D2 55
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#define R8A779H0_CLK_ZB3D4 56
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#define R8A779H0_CLK_ZG 57
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#define R8A779H0_CLK_SD0H 58
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#define R8A779H0_CLK_SD0 59
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#define R8A779H0_CLK_RPC 60
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#define R8A779H0_CLK_RPCD2 61
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#define R8A779H0_CLK_MSO 62
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#define R8A779H0_CLK_CANFD 63
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#define R8A779H0_CLK_CSI 64
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#define R8A779H0_CLK_FRAY 65
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#define R8A779H0_CLK_IPC 66
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#define R8A779H0_CLK_SASYNCRT 67
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#define R8A779H0_CLK_SASYNCPERD1 68
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#define R8A779H0_CLK_SASYNCPERD2 69
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#define R8A779H0_CLK_SASYNCPERD4 70
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#define R8A779H0_CLK_DSIEXT 71
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#define R8A779H0_CLK_DSIREF 72
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#define R8A779H0_CLK_ADGH 73
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#define R8A779H0_CLK_OSC 74
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#define R8A779H0_CLK_ZR0 75
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#define R8A779H0_CLK_ZR1 76
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#define R8A779H0_CLK_ZR2 77
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#define R8A779H0_CLK_RGMII 78
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#define R8A779H0_CLK_CPEX 79
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#define R8A779H0_CLK_CP 80
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#define R8A779H0_CLK_CBFUSA 81
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#define R8A779H0_CLK_R 82
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#endif /* __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__ */
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