65 lines
1.9 KiB
C
65 lines
1.9 KiB
C
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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/*
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* Copyright (C) 2021 Renesas Electronics Corp.
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*/
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#ifndef __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__
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#define __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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/* r8a779f0 CPG Core Clocks */
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#define R8A779F0_CLK_ZX 0
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#define R8A779F0_CLK_ZS 1
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#define R8A779F0_CLK_ZT 2
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#define R8A779F0_CLK_ZTR 3
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#define R8A779F0_CLK_S0D2 4
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#define R8A779F0_CLK_S0D3 5
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#define R8A779F0_CLK_S0D4 6
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#define R8A779F0_CLK_S0D2_MM 7
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#define R8A779F0_CLK_S0D3_MM 8
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#define R8A779F0_CLK_S0D4_MM 9
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#define R8A779F0_CLK_S0D2_RT 10
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#define R8A779F0_CLK_S0D3_RT 11
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#define R8A779F0_CLK_S0D4_RT 12
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#define R8A779F0_CLK_S0D6_RT 13
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#define R8A779F0_CLK_S0D3_PER 14
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#define R8A779F0_CLK_S0D6_PER 15
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#define R8A779F0_CLK_S0D12_PER 16
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#define R8A779F0_CLK_S0D24_PER 17
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#define R8A779F0_CLK_S0D2_HSC 18
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#define R8A779F0_CLK_S0D3_HSC 19
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#define R8A779F0_CLK_S0D4_HSC 20
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#define R8A779F0_CLK_S0D6_HSC 21
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#define R8A779F0_CLK_S0D12_HSC 22
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#define R8A779F0_CLK_S0D2_CC 23
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#define R8A779F0_CLK_CL 24
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#define R8A779F0_CLK_CL16M 25
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#define R8A779F0_CLK_CL16M_MM 26
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#define R8A779F0_CLK_CL16M_RT 27
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#define R8A779F0_CLK_CL16M_PER 28
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#define R8A779F0_CLK_CL16M_HSC 29
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#define R8A779F0_CLK_Z0 30
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#define R8A779F0_CLK_Z1 31
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#define R8A779F0_CLK_ZB3 32
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#define R8A779F0_CLK_ZB3D2 33
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#define R8A779F0_CLK_ZB3D4 34
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#define R8A779F0_CLK_SD0H 35
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#define R8A779F0_CLK_SD0 36
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#define R8A779F0_CLK_RPC 37
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#define R8A779F0_CLK_RPCD2 38
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#define R8A779F0_CLK_MSO 39
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#define R8A779F0_CLK_SASYNCRT 40
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#define R8A779F0_CLK_SASYNCPERD1 41
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#define R8A779F0_CLK_SASYNCPERD2 42
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#define R8A779F0_CLK_SASYNCPERD4 43
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#define R8A779F0_CLK_DBGSOC_HSC 44
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#define R8A779F0_CLK_RSW2 45
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#define R8A779F0_CLK_OSC 46
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#define R8A779F0_CLK_ZR 47
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#define R8A779F0_CLK_CPEX 48
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#define R8A779F0_CLK_CBFUSA 49
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#define R8A779F0_CLK_R 50
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#endif /* __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__ */
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