49 lines
1.3 KiB
C
49 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+
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*
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* Copyright (C) 2015 Renesas Electronics Corp.
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*/
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#ifndef __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
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#define __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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/* r8a7790 CPG Core Clocks */
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#define R8A7790_CLK_Z 0
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#define R8A7790_CLK_Z2 1
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#define R8A7790_CLK_ZG 2
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#define R8A7790_CLK_ZTR 3
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#define R8A7790_CLK_ZTRD2 4
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#define R8A7790_CLK_ZT 5
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#define R8A7790_CLK_ZX 6
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#define R8A7790_CLK_ZS 7
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#define R8A7790_CLK_HP 8
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#define R8A7790_CLK_I 9
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#define R8A7790_CLK_B 10
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#define R8A7790_CLK_LB 11
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#define R8A7790_CLK_P 12
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#define R8A7790_CLK_CL 13
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#define R8A7790_CLK_M2 14
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#define R8A7790_CLK_ADSP 15
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#define R8A7790_CLK_IMP 16
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#define R8A7790_CLK_ZB3 17
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#define R8A7790_CLK_ZB3D2 18
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#define R8A7790_CLK_DDR 19
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#define R8A7790_CLK_SDH 20
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#define R8A7790_CLK_SD0 21
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#define R8A7790_CLK_SD1 22
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#define R8A7790_CLK_SD2 23
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#define R8A7790_CLK_SD3 24
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#define R8A7790_CLK_MMC0 25
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#define R8A7790_CLK_MMC1 26
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#define R8A7790_CLK_MP 27
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#define R8A7790_CLK_SSP 28
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#define R8A7790_CLK_SSPRS 29
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#define R8A7790_CLK_QSPI 30
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#define R8A7790_CLK_CP 31
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#define R8A7790_CLK_RCAN 32
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#define R8A7790_CLK_R 33
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#define R8A7790_CLK_OSC 34
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#endif /* __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ */
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