486 lines
18 KiB
C
486 lines
18 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GCC_X1E80100_H
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#define _DT_BINDINGS_CLK_QCOM_GCC_X1E80100_H
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/* GCC clocks */
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#define GCC_AGGRE_NOC_USB_NORTH_AXI_CLK 0
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#define GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK 1
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#define GCC_AGGRE_UFS_PHY_AXI_CLK 2
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#define GCC_AGGRE_USB2_PRIM_AXI_CLK 3
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#define GCC_AGGRE_USB3_MP_AXI_CLK 4
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#define GCC_AGGRE_USB3_PRIM_AXI_CLK 5
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#define GCC_AGGRE_USB3_SEC_AXI_CLK 6
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#define GCC_AGGRE_USB3_TERT_AXI_CLK 7
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#define GCC_AGGRE_USB4_0_AXI_CLK 8
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#define GCC_AGGRE_USB4_1_AXI_CLK 9
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#define GCC_AGGRE_USB4_2_AXI_CLK 10
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#define GCC_AGGRE_USB_NOC_AXI_CLK 11
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#define GCC_AV1E_AHB_CLK 12
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#define GCC_AV1E_AXI_CLK 13
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#define GCC_AV1E_XO_CLK 14
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#define GCC_BOOT_ROM_AHB_CLK 15
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#define GCC_CAMERA_AHB_CLK 16
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#define GCC_CAMERA_HF_AXI_CLK 17
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#define GCC_CAMERA_SF_AXI_CLK 18
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#define GCC_CAMERA_XO_CLK 19
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#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 20
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#define GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK 21
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#define GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK 22
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#define GCC_CFG_NOC_USB2_PRIM_AXI_CLK 23
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#define GCC_CFG_NOC_USB3_MP_AXI_CLK 24
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#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 25
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#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 26
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#define GCC_CFG_NOC_USB3_TERT_AXI_CLK 27
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#define GCC_CFG_NOC_USB_ANOC_AHB_CLK 28
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#define GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK 29
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#define GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK 30
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#define GCC_CNOC_PCIE1_TUNNEL_CLK 31
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#define GCC_CNOC_PCIE2_TUNNEL_CLK 32
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#define GCC_CNOC_PCIE_NORTH_SF_AXI_CLK 33
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#define GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK 34
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#define GCC_CNOC_PCIE_TUNNEL_CLK 35
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#define GCC_DDRSS_GPU_AXI_CLK 36
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#define GCC_DISP_AHB_CLK 37
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#define GCC_DISP_HF_AXI_CLK 38
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#define GCC_DISP_XO_CLK 39
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#define GCC_GP1_CLK 40
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#define GCC_GP1_CLK_SRC 41
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#define GCC_GP2_CLK 42
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#define GCC_GP2_CLK_SRC 43
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#define GCC_GP3_CLK 44
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#define GCC_GP3_CLK_SRC 45
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#define GCC_GPLL0 46
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#define GCC_GPLL0_OUT_EVEN 47
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#define GCC_GPLL4 48
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#define GCC_GPLL7 49
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#define GCC_GPLL8 50
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#define GCC_GPLL9 51
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#define GCC_GPU_CFG_AHB_CLK 52
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#define GCC_GPU_GPLL0_CPH_CLK_SRC 53
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#define GCC_GPU_GPLL0_DIV_CPH_CLK_SRC 54
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#define GCC_GPU_MEMNOC_GFX_CLK 55
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#define GCC_GPU_SNOC_DVM_GFX_CLK 56
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#define GCC_PCIE0_PHY_RCHNG_CLK 57
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#define GCC_PCIE1_PHY_RCHNG_CLK 58
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#define GCC_PCIE2_PHY_RCHNG_CLK 59
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#define GCC_PCIE_0_AUX_CLK 60
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#define GCC_PCIE_0_AUX_CLK_SRC 61
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#define GCC_PCIE_0_CFG_AHB_CLK 62
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#define GCC_PCIE_0_MSTR_AXI_CLK 63
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#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 64
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#define GCC_PCIE_0_PIPE_CLK 65
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#define GCC_PCIE_0_SLV_AXI_CLK 66
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#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 67
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#define GCC_PCIE_1_AUX_CLK 68
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#define GCC_PCIE_1_AUX_CLK_SRC 69
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#define GCC_PCIE_1_CFG_AHB_CLK 70
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#define GCC_PCIE_1_MSTR_AXI_CLK 71
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#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 72
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#define GCC_PCIE_1_PIPE_CLK 73
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#define GCC_PCIE_1_SLV_AXI_CLK 74
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#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 75
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#define GCC_PCIE_2_AUX_CLK 76
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#define GCC_PCIE_2_AUX_CLK_SRC 77
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#define GCC_PCIE_2_CFG_AHB_CLK 78
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#define GCC_PCIE_2_MSTR_AXI_CLK 79
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#define GCC_PCIE_2_PHY_RCHNG_CLK_SRC 80
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#define GCC_PCIE_2_PIPE_CLK 81
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#define GCC_PCIE_2_SLV_AXI_CLK 82
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#define GCC_PCIE_2_SLV_Q2A_AXI_CLK 83
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#define GCC_PCIE_3_AUX_CLK 84
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#define GCC_PCIE_3_AUX_CLK_SRC 85
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#define GCC_PCIE_3_CFG_AHB_CLK 86
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#define GCC_PCIE_3_MSTR_AXI_CLK 87
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#define GCC_PCIE_3_PHY_AUX_CLK 88
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#define GCC_PCIE_3_PHY_RCHNG_CLK 89
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#define GCC_PCIE_3_PHY_RCHNG_CLK_SRC 90
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#define GCC_PCIE_3_PIPE_CLK 91
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#define GCC_PCIE_3_PIPE_DIV_CLK_SRC 92
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#define GCC_PCIE_3_PIPEDIV2_CLK 93
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#define GCC_PCIE_3_SLV_AXI_CLK 94
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#define GCC_PCIE_3_SLV_Q2A_AXI_CLK 95
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#define GCC_PCIE_4_AUX_CLK 96
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#define GCC_PCIE_4_AUX_CLK_SRC 97
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#define GCC_PCIE_4_CFG_AHB_CLK 98
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#define GCC_PCIE_4_MSTR_AXI_CLK 99
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#define GCC_PCIE_4_PHY_RCHNG_CLK 100
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#define GCC_PCIE_4_PHY_RCHNG_CLK_SRC 101
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#define GCC_PCIE_4_PIPE_CLK 102
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#define GCC_PCIE_4_PIPE_DIV_CLK_SRC 103
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#define GCC_PCIE_4_PIPEDIV2_CLK 104
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#define GCC_PCIE_4_SLV_AXI_CLK 105
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#define GCC_PCIE_4_SLV_Q2A_AXI_CLK 106
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#define GCC_PCIE_5_AUX_CLK 107
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#define GCC_PCIE_5_AUX_CLK_SRC 108
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#define GCC_PCIE_5_CFG_AHB_CLK 109
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#define GCC_PCIE_5_MSTR_AXI_CLK 110
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#define GCC_PCIE_5_PHY_RCHNG_CLK 111
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#define GCC_PCIE_5_PHY_RCHNG_CLK_SRC 112
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#define GCC_PCIE_5_PIPE_CLK 113
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#define GCC_PCIE_5_PIPE_DIV_CLK_SRC 114
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#define GCC_PCIE_5_PIPEDIV2_CLK 115
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#define GCC_PCIE_5_SLV_AXI_CLK 116
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#define GCC_PCIE_5_SLV_Q2A_AXI_CLK 117
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#define GCC_PCIE_6A_AUX_CLK 118
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#define GCC_PCIE_6A_AUX_CLK_SRC 119
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#define GCC_PCIE_6A_CFG_AHB_CLK 120
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#define GCC_PCIE_6A_MSTR_AXI_CLK 121
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#define GCC_PCIE_6A_PHY_AUX_CLK 122
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#define GCC_PCIE_6A_PHY_RCHNG_CLK 123
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#define GCC_PCIE_6A_PHY_RCHNG_CLK_SRC 124
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#define GCC_PCIE_6A_PIPE_CLK 125
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#define GCC_PCIE_6A_PIPE_DIV_CLK_SRC 126
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#define GCC_PCIE_6A_PIPEDIV2_CLK 127
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#define GCC_PCIE_6A_SLV_AXI_CLK 128
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#define GCC_PCIE_6A_SLV_Q2A_AXI_CLK 129
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#define GCC_PCIE_6B_AUX_CLK 130
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#define GCC_PCIE_6B_AUX_CLK_SRC 131
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#define GCC_PCIE_6B_CFG_AHB_CLK 132
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#define GCC_PCIE_6B_MSTR_AXI_CLK 133
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#define GCC_PCIE_6B_PHY_AUX_CLK 134
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#define GCC_PCIE_6B_PHY_RCHNG_CLK 135
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#define GCC_PCIE_6B_PHY_RCHNG_CLK_SRC 136
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#define GCC_PCIE_6B_PIPE_CLK 137
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#define GCC_PCIE_6B_PIPE_DIV_CLK_SRC 138
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#define GCC_PCIE_6B_PIPEDIV2_CLK 139
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#define GCC_PCIE_6B_SLV_AXI_CLK 140
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#define GCC_PCIE_6B_SLV_Q2A_AXI_CLK 141
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#define GCC_PCIE_RSCC_AHB_CLK 142
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#define GCC_PCIE_RSCC_XO_CLK 143
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#define GCC_PCIE_RSCC_XO_CLK_SRC 144
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#define GCC_PDM2_CLK 145
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#define GCC_PDM2_CLK_SRC 146
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#define GCC_PDM_AHB_CLK 147
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#define GCC_PDM_XO4_CLK 148
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#define GCC_QMIP_AV1E_AHB_CLK 149
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#define GCC_QMIP_CAMERA_NRT_AHB_CLK 150
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#define GCC_QMIP_CAMERA_RT_AHB_CLK 151
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#define GCC_QMIP_DISP_AHB_CLK 152
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#define GCC_QMIP_GPU_AHB_CLK 153
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#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 154
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#define GCC_QMIP_VIDEO_CVP_AHB_CLK 155
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#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 156
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#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 157
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#define GCC_QUPV3_WRAP0_CORE_2X_CLK 158
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#define GCC_QUPV3_WRAP0_CORE_CLK 159
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#define GCC_QUPV3_WRAP0_QSPI_S2_CLK 160
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#define GCC_QUPV3_WRAP0_QSPI_S3_CLK 161
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#define GCC_QUPV3_WRAP0_S0_CLK 162
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#define GCC_QUPV3_WRAP0_S0_CLK_SRC 163
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#define GCC_QUPV3_WRAP0_S1_CLK 164
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#define GCC_QUPV3_WRAP0_S1_CLK_SRC 165
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#define GCC_QUPV3_WRAP0_S2_CLK 166
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#define GCC_QUPV3_WRAP0_S2_CLK_SRC 167
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#define GCC_QUPV3_WRAP0_S2_DIV_CLK_SRC 168
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#define GCC_QUPV3_WRAP0_S3_CLK 169
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#define GCC_QUPV3_WRAP0_S3_CLK_SRC 170
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#define GCC_QUPV3_WRAP0_S3_DIV_CLK_SRC 171
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#define GCC_QUPV3_WRAP0_S4_CLK 172
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#define GCC_QUPV3_WRAP0_S4_CLK_SRC 173
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#define GCC_QUPV3_WRAP0_S5_CLK 174
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#define GCC_QUPV3_WRAP0_S5_CLK_SRC 175
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#define GCC_QUPV3_WRAP0_S6_CLK 176
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#define GCC_QUPV3_WRAP0_S6_CLK_SRC 177
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#define GCC_QUPV3_WRAP0_S7_CLK 178
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#define GCC_QUPV3_WRAP0_S7_CLK_SRC 179
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#define GCC_QUPV3_WRAP1_CORE_2X_CLK 180
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#define GCC_QUPV3_WRAP1_CORE_CLK 181
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#define GCC_QUPV3_WRAP1_QSPI_S2_CLK 182
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#define GCC_QUPV3_WRAP1_QSPI_S3_CLK 183
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#define GCC_QUPV3_WRAP1_S0_CLK 184
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#define GCC_QUPV3_WRAP1_S0_CLK_SRC 185
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#define GCC_QUPV3_WRAP1_S1_CLK 186
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#define GCC_QUPV3_WRAP1_S1_CLK_SRC 187
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#define GCC_QUPV3_WRAP1_S2_CLK 188
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#define GCC_QUPV3_WRAP1_S2_CLK_SRC 189
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#define GCC_QUPV3_WRAP1_S2_DIV_CLK_SRC 190
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#define GCC_QUPV3_WRAP1_S3_CLK 191
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#define GCC_QUPV3_WRAP1_S3_CLK_SRC 192
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#define GCC_QUPV3_WRAP1_S3_DIV_CLK_SRC 193
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#define GCC_QUPV3_WRAP1_S4_CLK 194
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#define GCC_QUPV3_WRAP1_S4_CLK_SRC 195
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#define GCC_QUPV3_WRAP1_S5_CLK 196
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#define GCC_QUPV3_WRAP1_S5_CLK_SRC 197
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#define GCC_QUPV3_WRAP1_S6_CLK 198
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#define GCC_QUPV3_WRAP1_S6_CLK_SRC 199
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#define GCC_QUPV3_WRAP1_S7_CLK 200
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#define GCC_QUPV3_WRAP1_S7_CLK_SRC 201
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#define GCC_QUPV3_WRAP2_CORE_2X_CLK 202
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#define GCC_QUPV3_WRAP2_CORE_CLK 203
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#define GCC_QUPV3_WRAP2_QSPI_S2_CLK 204
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#define GCC_QUPV3_WRAP2_QSPI_S3_CLK 205
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#define GCC_QUPV3_WRAP2_S0_CLK 206
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#define GCC_QUPV3_WRAP2_S0_CLK_SRC 207
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#define GCC_QUPV3_WRAP2_S1_CLK 208
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#define GCC_QUPV3_WRAP2_S1_CLK_SRC 209
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#define GCC_QUPV3_WRAP2_S2_CLK 210
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#define GCC_QUPV3_WRAP2_S2_CLK_SRC 211
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#define GCC_QUPV3_WRAP2_S2_DIV_CLK_SRC 212
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#define GCC_QUPV3_WRAP2_S3_CLK 213
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#define GCC_QUPV3_WRAP2_S3_CLK_SRC 214
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#define GCC_QUPV3_WRAP2_S3_DIV_CLK_SRC 215
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#define GCC_QUPV3_WRAP2_S4_CLK 216
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#define GCC_QUPV3_WRAP2_S4_CLK_SRC 217
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#define GCC_QUPV3_WRAP2_S5_CLK 218
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#define GCC_QUPV3_WRAP2_S5_CLK_SRC 219
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#define GCC_QUPV3_WRAP2_S6_CLK 220
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#define GCC_QUPV3_WRAP2_S6_CLK_SRC 221
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#define GCC_QUPV3_WRAP2_S7_CLK 222
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#define GCC_QUPV3_WRAP2_S7_CLK_SRC 223
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#define GCC_QUPV3_WRAP_0_M_AHB_CLK 224
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#define GCC_QUPV3_WRAP_0_S_AHB_CLK 225
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#define GCC_QUPV3_WRAP_1_M_AHB_CLK 226
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#define GCC_QUPV3_WRAP_1_S_AHB_CLK 227
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#define GCC_QUPV3_WRAP_2_M_AHB_CLK 228
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#define GCC_QUPV3_WRAP_2_S_AHB_CLK 229
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#define GCC_SDCC2_AHB_CLK 230
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#define GCC_SDCC2_APPS_CLK 231
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#define GCC_SDCC2_APPS_CLK_SRC 232
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#define GCC_SDCC4_AHB_CLK 233
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#define GCC_SDCC4_APPS_CLK 234
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#define GCC_SDCC4_APPS_CLK_SRC 235
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#define GCC_SYS_NOC_USB_AXI_CLK 236
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#define GCC_UFS_PHY_AHB_CLK 237
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#define GCC_UFS_PHY_AXI_CLK 238
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#define GCC_UFS_PHY_AXI_CLK_SRC 239
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#define GCC_UFS_PHY_ICE_CORE_CLK 240
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#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 241
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#define GCC_UFS_PHY_PHY_AUX_CLK 242
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#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 243
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#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 244
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#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 245
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#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 246
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK 247
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 248
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#define GCC_USB20_MASTER_CLK 249
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#define GCC_USB20_MASTER_CLK_SRC 250
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#define GCC_USB20_MOCK_UTMI_CLK 251
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#define GCC_USB20_MOCK_UTMI_CLK_SRC 252
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#define GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 253
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#define GCC_USB20_SLEEP_CLK 254
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#define GCC_USB30_MP_MASTER_CLK 255
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#define GCC_USB30_MP_MASTER_CLK_SRC 256
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#define GCC_USB30_MP_MOCK_UTMI_CLK 257
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#define GCC_USB30_MP_MOCK_UTMI_CLK_SRC 258
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#define GCC_USB30_MP_MOCK_UTMI_POSTDIV_CLK_SRC 259
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#define GCC_USB30_MP_SLEEP_CLK 260
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#define GCC_USB30_PRIM_MASTER_CLK 261
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#define GCC_USB30_PRIM_MASTER_CLK_SRC 262
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK 263
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 264
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#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 265
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#define GCC_USB30_PRIM_SLEEP_CLK 266
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#define GCC_USB30_SEC_MASTER_CLK 267
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#define GCC_USB30_SEC_MASTER_CLK_SRC 268
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#define GCC_USB30_SEC_MOCK_UTMI_CLK 269
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#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 270
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#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 271
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#define GCC_USB30_SEC_SLEEP_CLK 272
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#define GCC_USB30_TERT_MASTER_CLK 273
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#define GCC_USB30_TERT_MASTER_CLK_SRC 274
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#define GCC_USB30_TERT_MOCK_UTMI_CLK 275
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#define GCC_USB30_TERT_MOCK_UTMI_CLK_SRC 276
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#define GCC_USB30_TERT_MOCK_UTMI_POSTDIV_CLK_SRC 277
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#define GCC_USB30_TERT_SLEEP_CLK 278
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#define GCC_USB3_MP_PHY_AUX_CLK 279
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#define GCC_USB3_MP_PHY_AUX_CLK_SRC 280
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#define GCC_USB3_MP_PHY_COM_AUX_CLK 281
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#define GCC_USB3_MP_PHY_PIPE_0_CLK 282
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#define GCC_USB3_MP_PHY_PIPE_1_CLK 283
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#define GCC_USB3_PRIM_PHY_AUX_CLK 284
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#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 285
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#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 286
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#define GCC_USB3_PRIM_PHY_PIPE_CLK 287
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#define GCC_USB3_SEC_PHY_AUX_CLK 288
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#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 289
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#define GCC_USB3_SEC_PHY_COM_AUX_CLK 290
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#define GCC_USB3_SEC_PHY_PIPE_CLK 291
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#define GCC_USB3_TERT_PHY_AUX_CLK 292
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#define GCC_USB3_TERT_PHY_AUX_CLK_SRC 293
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#define GCC_USB3_TERT_PHY_COM_AUX_CLK 294
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#define GCC_USB3_TERT_PHY_PIPE_CLK 295
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#define GCC_USB4_0_CFG_AHB_CLK 296
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#define GCC_USB4_0_DP0_CLK 297
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#define GCC_USB4_0_DP1_CLK 298
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#define GCC_USB4_0_MASTER_CLK 299
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#define GCC_USB4_0_MASTER_CLK_SRC 300
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#define GCC_USB4_0_PHY_P2RR2P_PIPE_CLK 301
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#define GCC_USB4_0_PHY_PCIE_PIPE_CLK 302
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#define GCC_USB4_0_PHY_PCIE_PIPE_CLK_SRC 303
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#define GCC_USB4_0_PHY_RX0_CLK 304
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#define GCC_USB4_0_PHY_RX1_CLK 305
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#define GCC_USB4_0_PHY_USB_PIPE_CLK 306
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#define GCC_USB4_0_SB_IF_CLK 307
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#define GCC_USB4_0_SB_IF_CLK_SRC 308
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#define GCC_USB4_0_SYS_CLK 309
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#define GCC_USB4_0_TMU_CLK 310
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#define GCC_USB4_0_TMU_CLK_SRC 311
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#define GCC_USB4_1_CFG_AHB_CLK 312
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#define GCC_USB4_1_DP0_CLK 313
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#define GCC_USB4_1_DP1_CLK 314
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#define GCC_USB4_1_MASTER_CLK 315
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#define GCC_USB4_1_MASTER_CLK_SRC 316
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#define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK 317
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#define GCC_USB4_1_PHY_PCIE_PIPE_CLK 318
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#define GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC 319
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#define GCC_USB4_1_PHY_RX0_CLK 320
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#define GCC_USB4_1_PHY_RX1_CLK 321
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#define GCC_USB4_1_PHY_USB_PIPE_CLK 322
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#define GCC_USB4_1_SB_IF_CLK 323
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#define GCC_USB4_1_SB_IF_CLK_SRC 324
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#define GCC_USB4_1_SYS_CLK 325
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#define GCC_USB4_1_TMU_CLK 326
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#define GCC_USB4_1_TMU_CLK_SRC 327
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#define GCC_USB4_2_CFG_AHB_CLK 328
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#define GCC_USB4_2_DP0_CLK 329
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#define GCC_USB4_2_DP1_CLK 330
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#define GCC_USB4_2_MASTER_CLK 331
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#define GCC_USB4_2_MASTER_CLK_SRC 332
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#define GCC_USB4_2_PHY_P2RR2P_PIPE_CLK 333
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#define GCC_USB4_2_PHY_PCIE_PIPE_CLK 334
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#define GCC_USB4_2_PHY_PCIE_PIPE_CLK_SRC 335
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#define GCC_USB4_2_PHY_RX0_CLK 336
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#define GCC_USB4_2_PHY_RX1_CLK 337
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#define GCC_USB4_2_PHY_USB_PIPE_CLK 338
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#define GCC_USB4_2_SB_IF_CLK 339
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#define GCC_USB4_2_SB_IF_CLK_SRC 340
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#define GCC_USB4_2_SYS_CLK 341
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#define GCC_USB4_2_TMU_CLK 342
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#define GCC_USB4_2_TMU_CLK_SRC 343
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#define GCC_VIDEO_AHB_CLK 344
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#define GCC_VIDEO_AXI0_CLK 345
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#define GCC_VIDEO_AXI1_CLK 346
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#define GCC_VIDEO_XO_CLK 347
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#define GCC_PCIE_3_PIPE_CLK_SRC 348
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#define GCC_PCIE_4_PIPE_CLK_SRC 349
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#define GCC_PCIE_5_PIPE_CLK_SRC 350
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#define GCC_PCIE_6A_PIPE_CLK_SRC 351
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#define GCC_PCIE_6B_PIPE_CLK_SRC 352
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#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 353
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#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 354
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#define GCC_USB3_TERT_PHY_PIPE_CLK_SRC 355
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/* GCC power domains */
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#define GCC_PCIE_0_TUNNEL_GDSC 0
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#define GCC_PCIE_1_TUNNEL_GDSC 1
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#define GCC_PCIE_2_TUNNEL_GDSC 2
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#define GCC_PCIE_3_GDSC 3
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#define GCC_PCIE_3_PHY_GDSC 4
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#define GCC_PCIE_4_GDSC 5
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#define GCC_PCIE_4_PHY_GDSC 6
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#define GCC_PCIE_5_GDSC 7
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#define GCC_PCIE_5_PHY_GDSC 8
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#define GCC_PCIE_6_PHY_GDSC 9
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#define GCC_PCIE_6A_GDSC 10
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#define GCC_PCIE_6B_GDSC 11
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#define GCC_UFS_MEM_PHY_GDSC 12
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#define GCC_UFS_PHY_GDSC 13
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#define GCC_USB20_PRIM_GDSC 14
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#define GCC_USB30_MP_GDSC 15
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#define GCC_USB30_PRIM_GDSC 16
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#define GCC_USB30_SEC_GDSC 17
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#define GCC_USB30_TERT_GDSC 18
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#define GCC_USB3_MP_SS0_PHY_GDSC 19
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#define GCC_USB3_MP_SS1_PHY_GDSC 20
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#define GCC_USB4_0_GDSC 21
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#define GCC_USB4_1_GDSC 22
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#define GCC_USB4_2_GDSC 23
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#define GCC_USB_0_PHY_GDSC 24
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#define GCC_USB_1_PHY_GDSC 25
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#define GCC_USB_2_PHY_GDSC 26
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/* GCC resets */
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#define GCC_AV1E_BCR 0
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#define GCC_CAMERA_BCR 1
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#define GCC_DISPLAY_BCR 2
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#define GCC_GPU_BCR 3
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#define GCC_PCIE_0_LINK_DOWN_BCR 4
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#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5
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#define GCC_PCIE_0_PHY_BCR 6
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#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7
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#define GCC_PCIE_0_TUNNEL_BCR 8
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#define GCC_PCIE_1_LINK_DOWN_BCR 9
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#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 10
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#define GCC_PCIE_1_PHY_BCR 11
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#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 12
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#define GCC_PCIE_1_TUNNEL_BCR 13
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#define GCC_PCIE_2_LINK_DOWN_BCR 14
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#define GCC_PCIE_2_NOCSR_COM_PHY_BCR 15
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#define GCC_PCIE_2_PHY_BCR 16
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#define GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR 17
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#define GCC_PCIE_2_TUNNEL_BCR 18
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#define GCC_PCIE_3_BCR 19
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#define GCC_PCIE_3_LINK_DOWN_BCR 20
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#define GCC_PCIE_3_NOCSR_COM_PHY_BCR 21
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#define GCC_PCIE_3_PHY_BCR 22
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#define GCC_PCIE_3_PHY_NOCSR_COM_PHY_BCR 23
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#define GCC_PCIE_4_BCR 24
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#define GCC_PCIE_4_LINK_DOWN_BCR 25
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#define GCC_PCIE_4_NOCSR_COM_PHY_BCR 26
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#define GCC_PCIE_4_PHY_BCR 27
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#define GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR 28
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#define GCC_PCIE_5_BCR 29
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#define GCC_PCIE_5_LINK_DOWN_BCR 30
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#define GCC_PCIE_5_NOCSR_COM_PHY_BCR 31
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#define GCC_PCIE_5_PHY_BCR 32
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#define GCC_PCIE_5_PHY_NOCSR_COM_PHY_BCR 33
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#define GCC_PCIE_6A_BCR 34
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#define GCC_PCIE_6A_LINK_DOWN_BCR 35
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#define GCC_PCIE_6A_NOCSR_COM_PHY_BCR 36
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#define GCC_PCIE_6A_PHY_BCR 37
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|
#define GCC_PCIE_6A_PHY_NOCSR_COM_PHY_BCR 38
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|
#define GCC_PCIE_6B_BCR 39
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|
#define GCC_PCIE_6B_LINK_DOWN_BCR 40
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|
#define GCC_PCIE_6B_NOCSR_COM_PHY_BCR 41
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|
#define GCC_PCIE_6B_PHY_BCR 42
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|
#define GCC_PCIE_6B_PHY_NOCSR_COM_PHY_BCR 43
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|
#define GCC_PCIE_PHY_BCR 44
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|
#define GCC_PCIE_PHY_CFG_AHB_BCR 45
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#define GCC_PCIE_PHY_COM_BCR 46
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#define GCC_PCIE_RSCC_BCR 47
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#define GCC_PDM_BCR 48
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|
#define GCC_QUPV3_WRAPPER_0_BCR 49
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#define GCC_QUPV3_WRAPPER_1_BCR 50
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#define GCC_QUPV3_WRAPPER_2_BCR 51
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#define GCC_QUSB2PHY_HS0_MP_BCR 52
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#define GCC_QUSB2PHY_HS1_MP_BCR 53
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#define GCC_QUSB2PHY_PRIM_BCR 54
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|
#define GCC_QUSB2PHY_SEC_BCR 55
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|
#define GCC_QUSB2PHY_TERT_BCR 56
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#define GCC_QUSB2PHY_USB20_HS_BCR 57
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|
#define GCC_SDCC2_BCR 58
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|
#define GCC_SDCC4_BCR 59
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|
#define GCC_UFS_PHY_BCR 60
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#define GCC_USB20_PRIM_BCR 61
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#define GCC_USB30_MP_BCR 62
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|
#define GCC_USB30_PRIM_BCR 63
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|
#define GCC_USB30_SEC_BCR 64
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#define GCC_USB30_TERT_BCR 65
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|
#define GCC_USB3_MP_SS0_PHY_BCR 66
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|
#define GCC_USB3_MP_SS1_PHY_BCR 67
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#define GCC_USB3_PHY_PRIM_BCR 68
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#define GCC_USB3_PHY_SEC_BCR 69
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|
#define GCC_USB3_PHY_TERT_BCR 70
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|
#define GCC_USB3_UNIPHY_MP0_BCR 71
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|
#define GCC_USB3_UNIPHY_MP1_BCR 72
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|
#define GCC_USB3PHY_PHY_PRIM_BCR 73
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|
#define GCC_USB3PHY_PHY_SEC_BCR 74
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|
#define GCC_USB3PHY_PHY_TERT_BCR 75
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|
#define GCC_USB3UNIPHY_PHY_MP0_BCR 76
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|
#define GCC_USB3UNIPHY_PHY_MP1_BCR 77
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|
#define GCC_USB4_0_BCR 78
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|
#define GCC_USB4_0_DP0_PHY_PRIM_BCR 79
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|
#define GCC_USB4_1_DP0_PHY_SEC_BCR 80
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|
#define GCC_USB4_2_DP0_PHY_TERT_BCR 81
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|
#define GCC_USB4_1_BCR 82
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|
#define GCC_USB4_2_BCR 83
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|
#define GCC_USB_0_PHY_BCR 84
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|
#define GCC_USB_1_PHY_BCR 85
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#define GCC_USB_2_PHY_BCR 86
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|
#define GCC_VIDEO_BCR 87
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|
#endif
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