160 lines
		
	
	
		
			5.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			160 lines
		
	
	
		
			5.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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| /*
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|  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
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|  */
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| 
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| #ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8450_H
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| #define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8450_H
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| 
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| /* CAM_CC clocks */
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| #define CAM_CC_BPS_AHB_CLK					0
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| #define CAM_CC_BPS_CLK						1
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| #define CAM_CC_BPS_CLK_SRC					2
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| #define CAM_CC_BPS_FAST_AHB_CLK					3
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| #define CAM_CC_CAMNOC_AXI_CLK					4
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| #define CAM_CC_CAMNOC_AXI_CLK_SRC				5
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| #define CAM_CC_CAMNOC_DCD_XO_CLK				6
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| #define CAM_CC_CCI_0_CLK					7
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| #define CAM_CC_CCI_0_CLK_SRC					8
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| #define CAM_CC_CCI_1_CLK					9
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| #define CAM_CC_CCI_1_CLK_SRC					10
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| #define CAM_CC_CORE_AHB_CLK					11
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| #define CAM_CC_CPAS_AHB_CLK					12
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| #define CAM_CC_CPAS_BPS_CLK					13
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| #define CAM_CC_CPAS_FAST_AHB_CLK				14
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| #define CAM_CC_CPAS_IFE_0_CLK					15
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| #define CAM_CC_CPAS_IFE_1_CLK					16
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| #define CAM_CC_CPAS_IFE_2_CLK					17
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| #define CAM_CC_CPAS_IFE_LITE_CLK				18
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| #define CAM_CC_CPAS_IPE_NPS_CLK					19
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| #define CAM_CC_CPAS_SBI_CLK					20
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| #define CAM_CC_CPAS_SFE_0_CLK					21
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| #define CAM_CC_CPAS_SFE_1_CLK					22
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| #define CAM_CC_CPHY_RX_CLK_SRC					23
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| #define CAM_CC_CSI0PHYTIMER_CLK					24
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| #define CAM_CC_CSI0PHYTIMER_CLK_SRC				25
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| #define CAM_CC_CSI1PHYTIMER_CLK					26
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| #define CAM_CC_CSI1PHYTIMER_CLK_SRC				27
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| #define CAM_CC_CSI2PHYTIMER_CLK					28
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| #define CAM_CC_CSI2PHYTIMER_CLK_SRC				29
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| #define CAM_CC_CSI3PHYTIMER_CLK					30
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| #define CAM_CC_CSI3PHYTIMER_CLK_SRC				31
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| #define CAM_CC_CSI4PHYTIMER_CLK					32
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| #define CAM_CC_CSI4PHYTIMER_CLK_SRC				33
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| #define CAM_CC_CSI5PHYTIMER_CLK					34
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| #define CAM_CC_CSI5PHYTIMER_CLK_SRC				35
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| #define CAM_CC_CSID_CLK						36
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| #define CAM_CC_CSID_CLK_SRC					37
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| #define CAM_CC_CSID_CSIPHY_RX_CLK				38
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| #define CAM_CC_CSIPHY0_CLK					39
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| #define CAM_CC_CSIPHY1_CLK					40
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| #define CAM_CC_CSIPHY2_CLK					41
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| #define CAM_CC_CSIPHY3_CLK					42
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| #define CAM_CC_CSIPHY4_CLK					43
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| #define CAM_CC_CSIPHY5_CLK					44
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| #define CAM_CC_FAST_AHB_CLK_SRC					45
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| #define CAM_CC_GDSC_CLK						46
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| #define CAM_CC_ICP_AHB_CLK					47
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| #define CAM_CC_ICP_CLK						48
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| #define CAM_CC_ICP_CLK_SRC					49
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| #define CAM_CC_IFE_0_CLK					50
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| #define CAM_CC_IFE_0_CLK_SRC					51
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| #define CAM_CC_IFE_0_DSP_CLK					52
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| #define CAM_CC_IFE_0_FAST_AHB_CLK				53
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| #define CAM_CC_IFE_1_CLK					54
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| #define CAM_CC_IFE_1_CLK_SRC					55
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| #define CAM_CC_IFE_1_DSP_CLK					56
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| #define CAM_CC_IFE_1_FAST_AHB_CLK				57
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| #define CAM_CC_IFE_2_CLK					58
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| #define CAM_CC_IFE_2_CLK_SRC					59
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| #define CAM_CC_IFE_2_DSP_CLK					60
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| #define CAM_CC_IFE_2_FAST_AHB_CLK				61
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| #define CAM_CC_IFE_LITE_AHB_CLK					62
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| #define CAM_CC_IFE_LITE_CLK					63
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| #define CAM_CC_IFE_LITE_CLK_SRC					64
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| #define CAM_CC_IFE_LITE_CPHY_RX_CLK				65
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| #define CAM_CC_IFE_LITE_CSID_CLK				66
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| #define CAM_CC_IFE_LITE_CSID_CLK_SRC				67
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| #define CAM_CC_IPE_NPS_AHB_CLK					68
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| #define CAM_CC_IPE_NPS_CLK					69
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| #define CAM_CC_IPE_NPS_CLK_SRC					70
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| #define CAM_CC_IPE_NPS_FAST_AHB_CLK				71
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| #define CAM_CC_IPE_PPS_CLK					72
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| #define CAM_CC_IPE_PPS_FAST_AHB_CLK				73
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| #define CAM_CC_JPEG_CLK						74
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| #define CAM_CC_JPEG_CLK_SRC					75
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| #define CAM_CC_MCLK0_CLK					76
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| #define CAM_CC_MCLK0_CLK_SRC					77
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| #define CAM_CC_MCLK1_CLK					78
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| #define CAM_CC_MCLK1_CLK_SRC					79
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| #define CAM_CC_MCLK2_CLK					80
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| #define CAM_CC_MCLK2_CLK_SRC					81
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| #define CAM_CC_MCLK3_CLK					82
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| #define CAM_CC_MCLK3_CLK_SRC					83
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| #define CAM_CC_MCLK4_CLK					84
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| #define CAM_CC_MCLK4_CLK_SRC					85
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| #define CAM_CC_MCLK5_CLK					86
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| #define CAM_CC_MCLK5_CLK_SRC					87
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| #define CAM_CC_MCLK6_CLK					88
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| #define CAM_CC_MCLK6_CLK_SRC					89
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| #define CAM_CC_MCLK7_CLK					90
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| #define CAM_CC_MCLK7_CLK_SRC					91
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| #define CAM_CC_PLL0						92
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| #define CAM_CC_PLL0_OUT_EVEN					93
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| #define CAM_CC_PLL0_OUT_ODD					94
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| #define CAM_CC_PLL1						95
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| #define CAM_CC_PLL1_OUT_EVEN					96
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| #define CAM_CC_PLL2						97
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| #define CAM_CC_PLL3						98
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| #define CAM_CC_PLL3_OUT_EVEN					99
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| #define CAM_CC_PLL4						100
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| #define CAM_CC_PLL4_OUT_EVEN					101
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| #define CAM_CC_PLL5						102
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| #define CAM_CC_PLL5_OUT_EVEN					103
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| #define CAM_CC_PLL6						104
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| #define CAM_CC_PLL6_OUT_EVEN					105
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| #define CAM_CC_PLL7						106
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| #define CAM_CC_PLL7_OUT_EVEN					107
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| #define CAM_CC_PLL8						108
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| #define CAM_CC_PLL8_OUT_EVEN					109
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| #define CAM_CC_QDSS_DEBUG_CLK					110
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| #define CAM_CC_QDSS_DEBUG_CLK_SRC				111
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| #define CAM_CC_QDSS_DEBUG_XO_CLK				112
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| #define CAM_CC_SBI_AHB_CLK					113
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| #define CAM_CC_SBI_CLK						114
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| #define CAM_CC_SFE_0_CLK					115
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| #define CAM_CC_SFE_0_CLK_SRC					116
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| #define CAM_CC_SFE_0_FAST_AHB_CLK				117
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| #define CAM_CC_SFE_1_CLK					118
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| #define CAM_CC_SFE_1_CLK_SRC					119
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| #define CAM_CC_SFE_1_FAST_AHB_CLK				120
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| #define CAM_CC_SLEEP_CLK					121
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| #define CAM_CC_SLEEP_CLK_SRC					122
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| #define CAM_CC_SLOW_AHB_CLK_SRC					123
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| #define CAM_CC_XO_CLK_SRC					124
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| 
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| /* CAM_CC resets */
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| #define CAM_CC_BPS_BCR						0
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| #define CAM_CC_ICP_BCR						1
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| #define CAM_CC_IFE_0_BCR					2
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| #define CAM_CC_IFE_1_BCR					3
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| #define CAM_CC_IFE_2_BCR					4
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| #define CAM_CC_IPE_0_BCR					5
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| #define CAM_CC_QDSS_DEBUG_BCR					6
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| #define CAM_CC_SBI_BCR						7
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| #define CAM_CC_SFE_0_BCR					8
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| #define CAM_CC_SFE_1_BCR					9
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| 
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| /* CAM_CC GDSCRs */
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| #define BPS_GDSC		0
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| #define IPE_0_GDSC		1
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| #define SBI_GDSC		2
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| #define IFE_0_GDSC		3
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| #define IFE_1_GDSC		4
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| #define IFE_2_GDSC		5
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| #define SFE_0_GDSC		6
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| #define SFE_1_GDSC		7
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| #define TITAN_TOP_GDSC		8
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| 
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| #endif
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