52 lines
1.6 KiB
C
52 lines
1.6 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM4450_H
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#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM4450_H
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/* DISP_CC clocks */
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#define DISP_CC_MDSS_AHB1_CLK 0
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#define DISP_CC_MDSS_AHB_CLK 1
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#define DISP_CC_MDSS_AHB_CLK_SRC 2
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#define DISP_CC_MDSS_BYTE0_CLK 3
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#define DISP_CC_MDSS_BYTE0_CLK_SRC 4
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#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5
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#define DISP_CC_MDSS_BYTE0_INTF_CLK 6
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#define DISP_CC_MDSS_ESC0_CLK 7
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#define DISP_CC_MDSS_ESC0_CLK_SRC 8
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#define DISP_CC_MDSS_MDP1_CLK 9
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#define DISP_CC_MDSS_MDP_CLK 10
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#define DISP_CC_MDSS_MDP_CLK_SRC 11
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#define DISP_CC_MDSS_MDP_LUT1_CLK 12
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#define DISP_CC_MDSS_MDP_LUT_CLK 13
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#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 14
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#define DISP_CC_MDSS_PCLK0_CLK 15
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#define DISP_CC_MDSS_PCLK0_CLK_SRC 16
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#define DISP_CC_MDSS_ROT1_CLK 17
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#define DISP_CC_MDSS_ROT_CLK 18
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#define DISP_CC_MDSS_ROT_CLK_SRC 19
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#define DISP_CC_MDSS_RSCC_AHB_CLK 20
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#define DISP_CC_MDSS_RSCC_VSYNC_CLK 21
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#define DISP_CC_MDSS_VSYNC1_CLK 22
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#define DISP_CC_MDSS_VSYNC_CLK 23
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#define DISP_CC_MDSS_VSYNC_CLK_SRC 24
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#define DISP_CC_PLL0 25
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#define DISP_CC_PLL1 26
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#define DISP_CC_SLEEP_CLK 27
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#define DISP_CC_SLEEP_CLK_SRC 28
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#define DISP_CC_XO_CLK 29
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#define DISP_CC_XO_CLK_SRC 30
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/* DISP_CC power domains */
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#define DISP_CC_MDSS_CORE_GDSC 0
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#define DISP_CC_MDSS_CORE_INT2_GDSC 1
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/* DISP_CC resets */
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#define DISP_CC_MDSS_CORE_BCR 0
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#define DISP_CC_MDSS_CORE_INT2_BCR 1
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#define DISP_CC_MDSS_RSCC_BCR 2
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#endif
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