107 lines
3.4 KiB
C
107 lines
3.4 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM4450_H
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#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM4450_H
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/* CAM_CC clocks */
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#define CAM_CC_BPS_AHB_CLK 0
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#define CAM_CC_BPS_AREG_CLK 1
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#define CAM_CC_BPS_CLK 2
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#define CAM_CC_BPS_CLK_SRC 3
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#define CAM_CC_CAMNOC_ATB_CLK 4
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#define CAM_CC_CAMNOC_AXI_CLK 5
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#define CAM_CC_CAMNOC_AXI_CLK_SRC 6
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#define CAM_CC_CAMNOC_AXI_HF_CLK 7
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#define CAM_CC_CAMNOC_AXI_SF_CLK 8
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#define CAM_CC_CCI_0_CLK 9
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#define CAM_CC_CCI_0_CLK_SRC 10
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#define CAM_CC_CCI_1_CLK 11
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#define CAM_CC_CCI_1_CLK_SRC 12
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#define CAM_CC_CORE_AHB_CLK 13
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#define CAM_CC_CPAS_AHB_CLK 14
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#define CAM_CC_CPHY_RX_CLK_SRC 15
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#define CAM_CC_CRE_AHB_CLK 16
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#define CAM_CC_CRE_CLK 17
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#define CAM_CC_CRE_CLK_SRC 18
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#define CAM_CC_CSI0PHYTIMER_CLK 19
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#define CAM_CC_CSI0PHYTIMER_CLK_SRC 20
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#define CAM_CC_CSI1PHYTIMER_CLK 21
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#define CAM_CC_CSI1PHYTIMER_CLK_SRC 22
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#define CAM_CC_CSI2PHYTIMER_CLK 23
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#define CAM_CC_CSI2PHYTIMER_CLK_SRC 24
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#define CAM_CC_CSIPHY0_CLK 25
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#define CAM_CC_CSIPHY1_CLK 26
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#define CAM_CC_CSIPHY2_CLK 27
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#define CAM_CC_FAST_AHB_CLK_SRC 28
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#define CAM_CC_ICP_ATB_CLK 29
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#define CAM_CC_ICP_CLK 30
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#define CAM_CC_ICP_CLK_SRC 31
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#define CAM_CC_ICP_CTI_CLK 32
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#define CAM_CC_ICP_TS_CLK 33
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#define CAM_CC_MCLK0_CLK 34
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#define CAM_CC_MCLK0_CLK_SRC 35
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#define CAM_CC_MCLK1_CLK 36
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#define CAM_CC_MCLK1_CLK_SRC 37
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#define CAM_CC_MCLK2_CLK 38
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#define CAM_CC_MCLK2_CLK_SRC 39
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#define CAM_CC_MCLK3_CLK 40
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#define CAM_CC_MCLK3_CLK_SRC 41
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#define CAM_CC_OPE_0_AHB_CLK 42
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#define CAM_CC_OPE_0_AREG_CLK 43
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#define CAM_CC_OPE_0_CLK 44
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#define CAM_CC_OPE_0_CLK_SRC 45
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#define CAM_CC_PLL0 46
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#define CAM_CC_PLL0_OUT_EVEN 47
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#define CAM_CC_PLL0_OUT_ODD 48
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#define CAM_CC_PLL1 49
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#define CAM_CC_PLL1_OUT_EVEN 50
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#define CAM_CC_PLL2 51
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#define CAM_CC_PLL2_OUT_EVEN 52
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#define CAM_CC_PLL3 53
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#define CAM_CC_PLL3_OUT_EVEN 54
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#define CAM_CC_PLL4 55
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#define CAM_CC_PLL4_OUT_EVEN 56
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#define CAM_CC_SLOW_AHB_CLK_SRC 57
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#define CAM_CC_SOC_AHB_CLK 58
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#define CAM_CC_SYS_TMR_CLK 59
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#define CAM_CC_TFE_0_AHB_CLK 60
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#define CAM_CC_TFE_0_CLK 61
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#define CAM_CC_TFE_0_CLK_SRC 62
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#define CAM_CC_TFE_0_CPHY_RX_CLK 63
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#define CAM_CC_TFE_0_CSID_CLK 64
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#define CAM_CC_TFE_0_CSID_CLK_SRC 65
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#define CAM_CC_TFE_1_AHB_CLK 66
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#define CAM_CC_TFE_1_CLK 67
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#define CAM_CC_TFE_1_CLK_SRC 68
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#define CAM_CC_TFE_1_CPHY_RX_CLK 69
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#define CAM_CC_TFE_1_CSID_CLK 70
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#define CAM_CC_TFE_1_CSID_CLK_SRC 71
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/* CAM_CC power domains */
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#define CAM_CC_CAMSS_TOP_GDSC 0
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/* CAM_CC resets */
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#define CAM_CC_BPS_BCR 0
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#define CAM_CC_CAMNOC_BCR 1
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#define CAM_CC_CAMSS_TOP_BCR 2
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#define CAM_CC_CCI_0_BCR 3
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#define CAM_CC_CCI_1_BCR 4
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#define CAM_CC_CPAS_BCR 5
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#define CAM_CC_CRE_BCR 6
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#define CAM_CC_CSI0PHY_BCR 7
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#define CAM_CC_CSI1PHY_BCR 8
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#define CAM_CC_CSI2PHY_BCR 9
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#define CAM_CC_ICP_BCR 10
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#define CAM_CC_MCLK0_BCR 11
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#define CAM_CC_MCLK1_BCR 12
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#define CAM_CC_MCLK2_BCR 13
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#define CAM_CC_MCLK3_BCR 14
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#define CAM_CC_OPE_0_BCR 15
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#define CAM_CC_TFE_0_BCR 16
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#define CAM_CC_TFE_1_BCR 17
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#endif
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