166 lines
5.6 KiB
C
166 lines
5.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause */
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/*
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* Copyright (c) 2019-2020, Huawei Tech. Co., Ltd.
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*
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* Author: Dongjiu Geng <gengdongjiu@huawei.com>
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*/
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#ifndef __DTS_HI3559AV100_CLOCK_H
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#define __DTS_HI3559AV100_CLOCK_H
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/* fixed rate */
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#define HI3559AV100_FIXED_1188M 1
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#define HI3559AV100_FIXED_1000M 2
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#define HI3559AV100_FIXED_842M 3
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#define HI3559AV100_FIXED_792M 4
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#define HI3559AV100_FIXED_750M 5
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#define HI3559AV100_FIXED_710M 6
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#define HI3559AV100_FIXED_680M 7
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#define HI3559AV100_FIXED_667M 8
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#define HI3559AV100_FIXED_631M 9
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#define HI3559AV100_FIXED_600M 10
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#define HI3559AV100_FIXED_568M 11
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#define HI3559AV100_FIXED_500M 12
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#define HI3559AV100_FIXED_475M 13
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#define HI3559AV100_FIXED_428M 14
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#define HI3559AV100_FIXED_400M 15
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#define HI3559AV100_FIXED_396M 16
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#define HI3559AV100_FIXED_300M 17
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#define HI3559AV100_FIXED_250M 18
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#define HI3559AV100_FIXED_198M 19
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#define HI3559AV100_FIXED_187p5M 20
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#define HI3559AV100_FIXED_150M 21
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#define HI3559AV100_FIXED_148p5M 22
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#define HI3559AV100_FIXED_125M 23
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#define HI3559AV100_FIXED_107M 24
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#define HI3559AV100_FIXED_100M 25
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#define HI3559AV100_FIXED_99M 26
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#define HI3559AV100_FIXED_74p25M 27
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#define HI3559AV100_FIXED_72M 28
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#define HI3559AV100_FIXED_60M 29
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#define HI3559AV100_FIXED_54M 30
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#define HI3559AV100_FIXED_50M 31
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#define HI3559AV100_FIXED_49p5M 32
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#define HI3559AV100_FIXED_37p125M 33
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#define HI3559AV100_FIXED_36M 34
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#define HI3559AV100_FIXED_32p4M 35
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#define HI3559AV100_FIXED_27M 36
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#define HI3559AV100_FIXED_25M 37
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#define HI3559AV100_FIXED_24M 38
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#define HI3559AV100_FIXED_12M 39
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#define HI3559AV100_FIXED_3M 40
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#define HI3559AV100_FIXED_1p6M 41
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#define HI3559AV100_FIXED_400K 42
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#define HI3559AV100_FIXED_100K 43
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#define HI3559AV100_FIXED_200M 44
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#define HI3559AV100_FIXED_75M 75
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#define HI3559AV100_I2C0_CLK 50
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#define HI3559AV100_I2C1_CLK 51
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#define HI3559AV100_I2C2_CLK 52
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#define HI3559AV100_I2C3_CLK 53
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#define HI3559AV100_I2C4_CLK 54
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#define HI3559AV100_I2C5_CLK 55
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#define HI3559AV100_I2C6_CLK 56
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#define HI3559AV100_I2C7_CLK 57
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#define HI3559AV100_I2C8_CLK 58
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#define HI3559AV100_I2C9_CLK 59
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#define HI3559AV100_I2C10_CLK 60
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#define HI3559AV100_I2C11_CLK 61
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#define HI3559AV100_SPI0_CLK 62
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#define HI3559AV100_SPI1_CLK 63
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#define HI3559AV100_SPI2_CLK 64
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#define HI3559AV100_SPI3_CLK 65
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#define HI3559AV100_SPI4_CLK 66
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#define HI3559AV100_SPI5_CLK 67
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#define HI3559AV100_SPI6_CLK 68
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#define HI3559AV100_EDMAC_CLK 69
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#define HI3559AV100_EDMAC_AXICLK 70
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#define HI3559AV100_EDMAC1_CLK 71
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#define HI3559AV100_EDMAC1_AXICLK 72
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#define HI3559AV100_VDMAC_CLK 73
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/* mux clocks */
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#define HI3559AV100_FMC_MUX 80
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#define HI3559AV100_SYSAPB_MUX 81
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#define HI3559AV100_UART_MUX 82
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#define HI3559AV100_SYSBUS_MUX 83
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#define HI3559AV100_A73_MUX 84
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#define HI3559AV100_MMC0_MUX 85
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#define HI3559AV100_MMC1_MUX 86
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#define HI3559AV100_MMC2_MUX 87
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#define HI3559AV100_MMC3_MUX 88
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/* gate clocks */
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#define HI3559AV100_FMC_CLK 90
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#define HI3559AV100_UART0_CLK 91
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#define HI3559AV100_UART1_CLK 92
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#define HI3559AV100_UART2_CLK 93
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#define HI3559AV100_UART3_CLK 94
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#define HI3559AV100_UART4_CLK 95
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#define HI3559AV100_MMC0_CLK 96
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#define HI3559AV100_MMC1_CLK 97
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#define HI3559AV100_MMC2_CLK 98
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#define HI3559AV100_MMC3_CLK 99
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#define HI3559AV100_ETH_CLK 100
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#define HI3559AV100_ETH_MACIF_CLK 101
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#define HI3559AV100_ETH1_CLK 102
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#define HI3559AV100_ETH1_MACIF_CLK 103
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/* complex */
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#define HI3559AV100_MAC0_CLK 110
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#define HI3559AV100_MAC1_CLK 111
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#define HI3559AV100_SATA_CLK 112
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#define HI3559AV100_USB_CLK 113
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#define HI3559AV100_USB1_CLK 114
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/* pll clocks */
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#define HI3559AV100_APLL_CLK 250
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#define HI3559AV100_GPLL_CLK 251
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#define HI3559AV100_CRG_NR_CLKS 256
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#define HI3559AV100_SHUB_SOURCE_SOC_24M 0
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#define HI3559AV100_SHUB_SOURCE_SOC_200M 1
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#define HI3559AV100_SHUB_SOURCE_SOC_300M 2
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#define HI3559AV100_SHUB_SOURCE_PLL 3
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#define HI3559AV100_SHUB_SOURCE_CLK 4
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#define HI3559AV100_SHUB_I2C0_CLK 10
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#define HI3559AV100_SHUB_I2C1_CLK 11
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#define HI3559AV100_SHUB_I2C2_CLK 12
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#define HI3559AV100_SHUB_I2C3_CLK 13
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#define HI3559AV100_SHUB_I2C4_CLK 14
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#define HI3559AV100_SHUB_I2C5_CLK 15
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#define HI3559AV100_SHUB_I2C6_CLK 16
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#define HI3559AV100_SHUB_I2C7_CLK 17
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#define HI3559AV100_SHUB_SPI_SOURCE_CLK 20
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#define HI3559AV100_SHUB_SPI4_SOURCE_CLK 21
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#define HI3559AV100_SHUB_SPI0_CLK 22
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#define HI3559AV100_SHUB_SPI1_CLK 23
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#define HI3559AV100_SHUB_SPI2_CLK 24
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#define HI3559AV100_SHUB_SPI3_CLK 25
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#define HI3559AV100_SHUB_SPI4_CLK 26
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#define HI3559AV100_SHUB_UART_CLK_32K 30
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#define HI3559AV100_SHUB_UART_SOURCE_CLK 31
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#define HI3559AV100_SHUB_UART_DIV_CLK 32
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#define HI3559AV100_SHUB_UART0_CLK 33
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#define HI3559AV100_SHUB_UART1_CLK 34
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#define HI3559AV100_SHUB_UART2_CLK 35
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#define HI3559AV100_SHUB_UART3_CLK 36
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#define HI3559AV100_SHUB_UART4_CLK 37
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#define HI3559AV100_SHUB_UART5_CLK 38
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#define HI3559AV100_SHUB_UART6_CLK 39
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#define HI3559AV100_SHUB_EDMAC_CLK 40
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#define HI3559AV100_SHUB_NR_CLKS 50
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#endif /* __DTS_HI3559AV100_CLOCK_H */
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