373 lines
10 KiB
C
373 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2012 Avionic Design GmbH
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* Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
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*/
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#include <linux/clk.h>
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#include <linux/of.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_bridge_connector.h>
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#include <drm/drm_simple_kms_helper.h>
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#include "drm.h"
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#include "dc.h"
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struct tegra_rgb {
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struct tegra_output output;
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struct tegra_dc *dc;
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struct clk *pll_d_out0;
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struct clk *pll_d2_out0;
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struct clk *clk_parent;
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struct clk *clk;
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};
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static inline struct tegra_rgb *to_rgb(struct tegra_output *output)
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{
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return container_of(output, struct tegra_rgb, output);
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}
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struct reg_entry {
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unsigned long offset;
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unsigned long value;
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};
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static const struct reg_entry rgb_enable[] = {
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{ DC_COM_PIN_OUTPUT_ENABLE(0), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_ENABLE(1), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_ENABLE(2), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_ENABLE(3), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_POLARITY(1), 0x01000000 },
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{ DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_DATA(0), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_DATA(1), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_DATA(2), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_DATA(3), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_SELECT(4), 0x00210222 },
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{ DC_COM_PIN_OUTPUT_SELECT(5), 0x00002200 },
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{ DC_COM_PIN_OUTPUT_SELECT(6), 0x00020000 },
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};
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static const struct reg_entry rgb_disable[] = {
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{ DC_COM_PIN_OUTPUT_SELECT(6), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_SELECT(5), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_SELECT(4), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_DATA(3), 0xaaaaaaaa },
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{ DC_COM_PIN_OUTPUT_DATA(2), 0xaaaaaaaa },
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{ DC_COM_PIN_OUTPUT_DATA(1), 0xaaaaaaaa },
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{ DC_COM_PIN_OUTPUT_DATA(0), 0xaaaaaaaa },
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{ DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_POLARITY(1), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 },
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{ DC_COM_PIN_OUTPUT_ENABLE(3), 0x55555555 },
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{ DC_COM_PIN_OUTPUT_ENABLE(2), 0x55555555 },
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{ DC_COM_PIN_OUTPUT_ENABLE(1), 0x55150005 },
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{ DC_COM_PIN_OUTPUT_ENABLE(0), 0x55555555 },
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};
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static void tegra_dc_write_regs(struct tegra_dc *dc,
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const struct reg_entry *table,
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unsigned int num)
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{
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unsigned int i;
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for (i = 0; i < num; i++)
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tegra_dc_writel(dc, table[i].value, table[i].offset);
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}
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static void tegra_rgb_encoder_disable(struct drm_encoder *encoder)
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{
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struct tegra_output *output = encoder_to_output(encoder);
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struct tegra_rgb *rgb = to_rgb(output);
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tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable));
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tegra_dc_commit(rgb->dc);
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}
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static void tegra_rgb_encoder_enable(struct drm_encoder *encoder)
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{
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struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
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struct tegra_output *output = encoder_to_output(encoder);
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struct tegra_rgb *rgb = to_rgb(output);
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u32 value;
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tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable));
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value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL;
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tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS);
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/* configure H- and V-sync signal polarities */
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value = tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1));
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if (mode->flags & DRM_MODE_FLAG_NHSYNC)
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value |= LHS_OUTPUT_POLARITY_LOW;
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else
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value &= ~LHS_OUTPUT_POLARITY_LOW;
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if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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value |= LVS_OUTPUT_POLARITY_LOW;
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else
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value &= ~LVS_OUTPUT_POLARITY_LOW;
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tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1));
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/* XXX: parameterize? */
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value = DISP_DATA_FORMAT_DF1P1C | DISP_ALIGNMENT_MSB |
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DISP_ORDER_RED_BLUE;
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tegra_dc_writel(rgb->dc, value, DC_DISP_DISP_INTERFACE_CONTROL);
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tegra_dc_commit(rgb->dc);
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}
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static bool tegra_rgb_pll_rate_change_allowed(struct tegra_rgb *rgb)
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{
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if (!rgb->pll_d2_out0)
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return false;
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if (!clk_is_match(rgb->clk_parent, rgb->pll_d_out0) &&
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!clk_is_match(rgb->clk_parent, rgb->pll_d2_out0))
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return false;
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return true;
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}
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static int
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tegra_rgb_encoder_atomic_check(struct drm_encoder *encoder,
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struct drm_crtc_state *crtc_state,
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struct drm_connector_state *conn_state)
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{
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struct tegra_output *output = encoder_to_output(encoder);
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struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
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unsigned long pclk = crtc_state->mode.clock * 1000;
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struct tegra_rgb *rgb = to_rgb(output);
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unsigned int div;
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int err;
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/*
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* We may not want to change the frequency of the parent clock, since
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* it may be a parent for other peripherals. This is due to the fact
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* that on Tegra20 there's only a single clock dedicated to display
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* (pll_d_out0), whereas later generations have a second one that can
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* be used to independently drive a second output (pll_d2_out0).
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*
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* As a way to support multiple outputs on Tegra20 as well, pll_p is
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* typically used as the parent clock for the display controllers.
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* But this comes at a cost: pll_p is the parent of several other
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* peripherals, so its frequency shouldn't change out of the blue.
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*
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* The best we can do at this point is to use the shift clock divider
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* and hope that the desired frequency can be matched (or at least
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* matched sufficiently close that the panel will still work).
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*/
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if (tegra_rgb_pll_rate_change_allowed(rgb)) {
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/*
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* Set display controller clock to x2 of PCLK in order to
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* produce higher resolution pulse positions.
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*/
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div = 2;
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pclk *= 2;
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} else {
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div = ((clk_get_rate(rgb->clk) * 2) / pclk) - 2;
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pclk = 0;
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}
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err = tegra_dc_state_setup_clock(dc, crtc_state, rgb->clk_parent,
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pclk, div);
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if (err < 0) {
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dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
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return err;
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}
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return err;
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}
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static const struct drm_encoder_helper_funcs tegra_rgb_encoder_helper_funcs = {
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.disable = tegra_rgb_encoder_disable,
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.enable = tegra_rgb_encoder_enable,
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.atomic_check = tegra_rgb_encoder_atomic_check,
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};
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int tegra_dc_rgb_probe(struct tegra_dc *dc)
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{
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struct device_node *np;
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struct tegra_rgb *rgb;
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int err;
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np = of_get_child_by_name(dc->dev->of_node, "rgb");
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if (!np || !of_device_is_available(np))
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return -ENODEV;
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rgb = devm_kzalloc(dc->dev, sizeof(*rgb), GFP_KERNEL);
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if (!rgb)
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return -ENOMEM;
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rgb->output.dev = dc->dev;
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rgb->output.of_node = np;
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rgb->dc = dc;
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err = tegra_output_probe(&rgb->output);
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if (err < 0)
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return err;
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rgb->clk = devm_clk_get(dc->dev, NULL);
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if (IS_ERR(rgb->clk)) {
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dev_err(dc->dev, "failed to get clock\n");
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err = PTR_ERR(rgb->clk);
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goto remove;
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}
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rgb->clk_parent = devm_clk_get(dc->dev, "parent");
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if (IS_ERR(rgb->clk_parent)) {
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dev_err(dc->dev, "failed to get parent clock\n");
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err = PTR_ERR(rgb->clk_parent);
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goto remove;
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}
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err = clk_set_parent(rgb->clk, rgb->clk_parent);
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if (err < 0) {
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dev_err(dc->dev, "failed to set parent clock: %d\n", err);
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goto remove;
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}
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rgb->pll_d_out0 = clk_get_sys(NULL, "pll_d_out0");
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if (IS_ERR(rgb->pll_d_out0)) {
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err = PTR_ERR(rgb->pll_d_out0);
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dev_err(dc->dev, "failed to get pll_d_out0: %d\n", err);
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goto remove;
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}
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if (dc->soc->has_pll_d2_out0) {
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rgb->pll_d2_out0 = clk_get_sys(NULL, "pll_d2_out0");
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if (IS_ERR(rgb->pll_d2_out0)) {
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err = PTR_ERR(rgb->pll_d2_out0);
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dev_err(dc->dev, "failed to get pll_d2_out0: %d\n", err);
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goto put_pll;
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}
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}
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dc->rgb = &rgb->output;
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return 0;
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put_pll:
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clk_put(rgb->pll_d_out0);
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remove:
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tegra_output_remove(&rgb->output);
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return err;
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}
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void tegra_dc_rgb_remove(struct tegra_dc *dc)
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{
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struct tegra_rgb *rgb;
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if (!dc->rgb)
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return;
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rgb = to_rgb(dc->rgb);
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clk_put(rgb->pll_d2_out0);
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clk_put(rgb->pll_d_out0);
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tegra_output_remove(dc->rgb);
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dc->rgb = NULL;
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}
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int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc)
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{
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struct tegra_output *output = dc->rgb;
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struct drm_connector *connector;
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int err;
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if (!dc->rgb)
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return -ENODEV;
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drm_simple_encoder_init(drm, &output->encoder, DRM_MODE_ENCODER_LVDS);
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drm_encoder_helper_add(&output->encoder,
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&tegra_rgb_encoder_helper_funcs);
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/*
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* Wrap directly-connected panel into DRM bridge in order to let
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* DRM core to handle panel for us.
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*/
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if (output->panel) {
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output->bridge = devm_drm_panel_bridge_add(output->dev,
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output->panel);
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if (IS_ERR(output->bridge)) {
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dev_err(output->dev,
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"failed to wrap panel into bridge: %pe\n",
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output->bridge);
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return PTR_ERR(output->bridge);
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}
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output->panel = NULL;
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}
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/*
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* Tegra devices that have LVDS panel utilize LVDS encoder bridge
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* for converting up to 28 LCD LVTTL lanes into 5/4 LVDS lanes that
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* go to display panel's receiver.
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*
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* Encoder usually have a power-down control which needs to be enabled
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* in order to transmit data to the panel. Historically devices that
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* use an older device-tree version didn't model the bridge, assuming
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* that encoder is turned ON by default, while today's DRM allows us
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* to model LVDS encoder properly.
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*
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* Newer device-trees utilize LVDS encoder bridge, which provides
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* us with a connector and handles the display panel.
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*
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* For older device-trees we wrapped panel into the panel-bridge.
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*/
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if (output->bridge) {
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err = drm_bridge_attach(&output->encoder, output->bridge,
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NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR);
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if (err)
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return err;
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connector = drm_bridge_connector_init(drm, &output->encoder);
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if (IS_ERR(connector)) {
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dev_err(output->dev,
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"failed to initialize bridge connector: %pe\n",
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connector);
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return PTR_ERR(connector);
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}
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drm_connector_attach_encoder(connector, &output->encoder);
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}
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err = tegra_output_init(drm, output);
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if (err < 0) {
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dev_err(output->dev, "failed to initialize output: %d\n", err);
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return err;
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}
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/*
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* Other outputs can be attached to either display controller. The RGB
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* outputs are an exception and work only with their parent display
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* controller.
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*/
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output->encoder.possible_crtcs = drm_crtc_mask(&dc->base);
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return 0;
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}
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int tegra_dc_rgb_exit(struct tegra_dc *dc)
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{
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if (dc->rgb)
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tegra_output_exit(dc->rgb);
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return 0;
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}
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