709 lines
31 KiB
C
709 lines
31 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Driver for AMD network controllers and boards
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*
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* Copyright (C) 2021, Xilinx, Inc.
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* Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
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*/
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#ifndef MC_CDX_PCOL_H
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#define MC_CDX_PCOL_H
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/* The current version of the MCDI protocol. */
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#define MCDI_PCOL_VERSION 2
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/*
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* Each MCDI request starts with an MCDI_HEADER, which is a 32bit
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* structure, filled in by the client.
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*
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* 0 7 8 16 20 22 23 24 31
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* | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS |
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* | | |
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* | | \--- Response
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* | \------- Error
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* \------------------------------ Resync (always set)
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*
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* The client writes its request into MC shared memory, and rings the
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* doorbell. Each request is completed either by the MC writing
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* back into shared memory, or by writing out an event.
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*
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* All MCDI commands support completion by shared memory response. Each
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* request may also contain additional data (accounted for by HEADER.LEN),
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* and some responses may also contain additional data (again, accounted
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* for by HEADER.LEN).
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*
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* Some MCDI commands support completion by event, in which any associated
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* response data is included in the event.
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*
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* The protocol requires one response to be delivered for every request; a
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* request should not be sent unless the response for the previous request
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* has been received (either by polling shared memory, or by receiving
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* an event).
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*/
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/** Request/Response structure */
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#define MCDI_HEADER_OFST 0
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#define MCDI_HEADER_CODE_LBN 0
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#define MCDI_HEADER_CODE_WIDTH 7
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#define MCDI_HEADER_RESYNC_LBN 7
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#define MCDI_HEADER_RESYNC_WIDTH 1
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#define MCDI_HEADER_DATALEN_LBN 8
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#define MCDI_HEADER_DATALEN_WIDTH 8
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#define MCDI_HEADER_SEQ_LBN 16
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#define MCDI_HEADER_SEQ_WIDTH 4
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#define MCDI_HEADER_RSVD_LBN 20
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#define MCDI_HEADER_RSVD_WIDTH 1
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#define MCDI_HEADER_NOT_EPOCH_LBN 21
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#define MCDI_HEADER_NOT_EPOCH_WIDTH 1
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#define MCDI_HEADER_ERROR_LBN 22
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#define MCDI_HEADER_ERROR_WIDTH 1
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#define MCDI_HEADER_RESPONSE_LBN 23
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#define MCDI_HEADER_RESPONSE_WIDTH 1
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#define MCDI_HEADER_XFLAGS_LBN 24
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#define MCDI_HEADER_XFLAGS_WIDTH 8
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/* Request response using event */
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#define MCDI_HEADER_XFLAGS_EVREQ 0x01
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/* Request (and signal) early doorbell return */
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#define MCDI_HEADER_XFLAGS_DBRET 0x02
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/* Maximum number of payload bytes */
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#define MCDI_CTL_SDU_LEN_MAX_V2 0x400
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#define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V2
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/*
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* The MC can generate events for two reasons:
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* - To advance a shared memory request if XFLAGS_EVREQ was set
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* - As a notification (link state, i2c event), controlled
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* via MC_CMD_LOG_CTRL
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*
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* Both events share a common structure:
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*
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* 0 32 33 36 44 52 60
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* | Data | Cont | Level | Src | Code | Rsvd |
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* |
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* \ There is another event pending in this notification
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*
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* If Code==CMDDONE, then the fields are further interpreted as:
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*
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* - LEVEL==INFO Command succeeded
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* - LEVEL==ERR Command failed
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*
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* 0 8 16 24 32
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* | Seq | Datalen | Errno | Rsvd |
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*
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* These fields are taken directly out of the standard MCDI header, i.e.,
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* LEVEL==ERR, Datalen == 0 => Reboot
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*
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* Events can be squirted out of the UART (using LOG_CTRL) without a
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* MCDI header. An event can be distinguished from a MCDI response by
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* examining the first byte which is 0xc0. This corresponds to the
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* non-existent MCDI command MC_CMD_DEBUG_LOG.
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*
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* 0 7 8
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* | command | Resync | = 0xc0
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*
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* Since the event is written in big-endian byte order, this works
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* providing bits 56-63 of the event are 0xc0.
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*
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* 56 60 63
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* | Rsvd | Code | = 0xc0
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*
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* Which means for convenience the event code is 0xc for all MC
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* generated events.
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*/
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/*
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* the errno value may be followed by the (0-based) number of the
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* first argument that could not be processed.
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*/
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#define MC_CMD_ERR_ARG_OFST 4
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/* MC_CMD_ERR MCDI error codes. */
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/* Operation not permitted. */
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#define MC_CMD_ERR_EPERM 0x1
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/* Non-existent command target */
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#define MC_CMD_ERR_ENOENT 0x2
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/* assert() has killed the MC */
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#define MC_CMD_ERR_EINTR 0x4
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/* I/O failure */
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#define MC_CMD_ERR_EIO 0x5
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/* Already exists */
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#define MC_CMD_ERR_EEXIST 0x6
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/* Try again */
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#define MC_CMD_ERR_EAGAIN 0xb
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/* Out of memory */
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#define MC_CMD_ERR_ENOMEM 0xc
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/* Caller does not hold required locks */
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#define MC_CMD_ERR_EACCES 0xd
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/* Resource is currently unavailable (e.g. lock contention) */
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#define MC_CMD_ERR_EBUSY 0x10
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/* No such device */
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#define MC_CMD_ERR_ENODEV 0x13
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/* Invalid argument to target */
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#define MC_CMD_ERR_EINVAL 0x16
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/* No space */
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#define MC_CMD_ERR_ENOSPC 0x1c
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/* Read-only */
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#define MC_CMD_ERR_EROFS 0x1e
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/* Broken pipe */
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#define MC_CMD_ERR_EPIPE 0x20
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/* Out of range */
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#define MC_CMD_ERR_ERANGE 0x22
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/* Non-recursive resource is already acquired */
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#define MC_CMD_ERR_EDEADLK 0x23
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/* Operation not implemented */
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#define MC_CMD_ERR_ENOSYS 0x26
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/* Operation timed out */
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#define MC_CMD_ERR_ETIME 0x3e
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/* Link has been severed */
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#define MC_CMD_ERR_ENOLINK 0x43
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/* Protocol error */
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#define MC_CMD_ERR_EPROTO 0x47
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/* Bad message */
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#define MC_CMD_ERR_EBADMSG 0x4a
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/* Operation not supported */
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#define MC_CMD_ERR_ENOTSUP 0x5f
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/* Address not available */
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#define MC_CMD_ERR_EADDRNOTAVAIL 0x63
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/* Not connected */
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#define MC_CMD_ERR_ENOTCONN 0x6b
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/* Operation already in progress */
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#define MC_CMD_ERR_EALREADY 0x72
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/* Stale handle. The handle references resource that no longer exists */
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#define MC_CMD_ERR_ESTALE 0x74
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/* Resource allocation failed. */
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#define MC_CMD_ERR_ALLOC_FAIL 0x1000
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/* V-adaptor not found. */
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#define MC_CMD_ERR_NO_VADAPTOR 0x1001
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/* EVB port not found. */
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#define MC_CMD_ERR_NO_EVB_PORT 0x1002
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/* V-switch not found. */
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#define MC_CMD_ERR_NO_VSWITCH 0x1003
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/* Too many VLAN tags. */
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#define MC_CMD_ERR_VLAN_LIMIT 0x1004
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/* Bad PCI function number. */
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#define MC_CMD_ERR_BAD_PCI_FUNC 0x1005
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/* Invalid VLAN mode. */
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#define MC_CMD_ERR_BAD_VLAN_MODE 0x1006
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/* Invalid v-switch type. */
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#define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007
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/* Invalid v-port type. */
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#define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008
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/* MAC address exists. */
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#define MC_CMD_ERR_MAC_EXIST 0x1009
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/* Slave core not present */
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#define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a
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/* The datapath is disabled. */
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#define MC_CMD_ERR_DATAPATH_DISABLED 0x100b
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/* The requesting client is not a function */
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#define MC_CMD_ERR_CLIENT_NOT_FN 0x100c
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/*
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* The requested operation might require the command to be passed between
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* MCs, and the transport doesn't support that. Should only ever been seen over
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* the UART.
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*/
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#define MC_CMD_ERR_NO_PRIVILEGE 0x1013
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/*
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* Workaround 26807 could not be turned on/off because some functions
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* have already installed filters. See the comment at
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* MC_CMD_WORKAROUND_BUG26807. May also returned for other operations such as
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* sub-variant switching.
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*/
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#define MC_CMD_ERR_FILTERS_PRESENT 0x1014
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/* The clock whose frequency you've attempted to set doesn't exist */
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#define MC_CMD_ERR_NO_CLOCK 0x1015
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/*
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* Returned by MC_CMD_TESTASSERT if the action that should have caused an
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* assertion failed to do so.
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*/
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#define MC_CMD_ERR_UNREACHABLE 0x1016
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/*
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* This command needs to be processed in the background but there were no
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* resources to do so. Send it again after a command has completed.
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*/
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#define MC_CMD_ERR_QUEUE_FULL 0x1017
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/*
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* The operation could not be completed because the PCIe link has gone
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* away. This error code is never expected to be returned over the TLP
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* transport.
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*/
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#define MC_CMD_ERR_NO_PCIE 0x1018
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/*
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* The operation could not be completed because the datapath has gone
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* away. This is distinct from MC_CMD_ERR_DATAPATH_DISABLED in that the
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* datapath absence may be temporary
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*/
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#define MC_CMD_ERR_NO_DATAPATH 0x1019
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/* The operation could not complete because some VIs are allocated */
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#define MC_CMD_ERR_VIS_PRESENT 0x101a
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/*
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* The operation could not complete because some PIO buffers are
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* allocated
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*/
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#define MC_CMD_ERR_PIOBUFS_PRESENT 0x101b
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/***********************************/
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/*
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* MC_CMD_CDX_BUS_ENUM_BUSES
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* CDX bus hosts devices (functions) that are implemented using the Composable
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* DMA subsystem and directly mapped into the memory space of the FGPA PSX
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* Application Processors (APUs). As such, they only apply to the PSX APU side,
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* not the host (PCIe). Unlike PCIe, these devices have no native configuration
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* space or enumeration mechanism, so this message set provides a minimal
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* interface for discovery and management (bus reset, FLR, BME) of such
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* devices. This command returns the number of CDX buses present in the system.
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*/
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#define MC_CMD_CDX_BUS_ENUM_BUSES 0x1
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#define MC_CMD_CDX_BUS_ENUM_BUSES_MSGSET 0x1
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#undef MC_CMD_0x1_PRIVILEGE_CTG
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#define MC_CMD_0x1_PRIVILEGE_CTG SRIOV_CTG_ADMIN
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/* MC_CMD_CDX_BUS_ENUM_BUSES_IN msgrequest */
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#define MC_CMD_CDX_BUS_ENUM_BUSES_IN_LEN 0
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/* MC_CMD_CDX_BUS_ENUM_BUSES_OUT msgresponse */
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#define MC_CMD_CDX_BUS_ENUM_BUSES_OUT_LEN 4
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/*
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* Number of CDX buses present in the system. Buses are numbered 0 to
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* BUS_COUNT-1
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*/
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#define MC_CMD_CDX_BUS_ENUM_BUSES_OUT_BUS_COUNT_OFST 0
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#define MC_CMD_CDX_BUS_ENUM_BUSES_OUT_BUS_COUNT_LEN 4
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/***********************************/
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/*
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* MC_CMD_CDX_BUS_ENUM_DEVICES
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* Enumerate CDX bus devices on a given bus
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*/
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#define MC_CMD_CDX_BUS_ENUM_DEVICES 0x2
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#define MC_CMD_CDX_BUS_ENUM_DEVICES_MSGSET 0x2
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#undef MC_CMD_0x2_PRIVILEGE_CTG
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#define MC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_ADMIN
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/* MC_CMD_CDX_BUS_ENUM_DEVICES_IN msgrequest */
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#define MC_CMD_CDX_BUS_ENUM_DEVICES_IN_LEN 4
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/*
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* Bus number to enumerate, in range 0 to BUS_COUNT-1, as returned by
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* MC_CMD_CDX_BUS_ENUM_BUSES_OUT
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*/
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#define MC_CMD_CDX_BUS_ENUM_DEVICES_IN_BUS_OFST 0
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#define MC_CMD_CDX_BUS_ENUM_DEVICES_IN_BUS_LEN 4
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/* MC_CMD_CDX_BUS_ENUM_DEVICES_OUT msgresponse */
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#define MC_CMD_CDX_BUS_ENUM_DEVICES_OUT_LEN 4
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/*
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* Number of devices present on the bus. Devices on the bus are numbered 0 to
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* DEVICE_COUNT-1. Returns EAGAIN if number of devices unknown or if the target
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* devices are not ready (e.g. undergoing a bus reset)
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*/
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#define MC_CMD_CDX_BUS_ENUM_DEVICES_OUT_DEVICE_COUNT_OFST 0
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#define MC_CMD_CDX_BUS_ENUM_DEVICES_OUT_DEVICE_COUNT_LEN 4
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/***********************************/
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/*
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* MC_CMD_CDX_BUS_GET_DEVICE_CONFIG
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* Returns device identification and MMIO/MSI resource data for a CDX device.
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* The expected usage is for the caller to first retrieve the number of devices
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* on the bus using MC_CMD_BUS_ENUM_DEVICES, then loop through the range (0,
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* DEVICE_COUNT - 1), retrieving device resource data. May return EAGAIN if the
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* number of exposed devices or device resources change during enumeration (due
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* to e.g. a PL reload / bus reset), in which case the caller is expected to
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* restart the enumeration loop. MMIO addresses are specified in terms of bus
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* addresses (prior to any potential IOMMU translation). For versal-net, these
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* are equivalent to APU physical addresses. Implementation note - for this to
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* work, the implementation needs to keep state (generation count) per client.
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*/
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG 0x3
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_MSGSET 0x3
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#undef MC_CMD_0x3_PRIVILEGE_CTG
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#define MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN
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/* MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_IN msgrequest */
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_IN_LEN 8
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/* Device bus number, in range 0 to BUS_COUNT-1 */
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_IN_BUS_OFST 0
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_IN_BUS_LEN 4
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/* Device number relative to the bus, in range 0 to DEVICE_COUNT-1 for that bus */
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_IN_DEVICE_OFST 4
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_IN_DEVICE_LEN 4
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/* MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT msgresponse */
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_LEN 88
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/* 16-bit Vendor identifier, compliant with PCI-SIG VendorID assignment. */
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_VENDOR_ID_OFST 0
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_VENDOR_ID_LEN 2
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/* 16-bit Device ID assigned by the vendor */
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_DEVICE_ID_OFST 2
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_DEVICE_ID_LEN 2
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/*
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* 16-bit Subsystem Vendor ID, , compliant with PCI-SIG VendorID assignment.
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* For further device differentiation, as required. 0 if unused.
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*/
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_SUBSYS_VENDOR_ID_OFST 4
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_SUBSYS_VENDOR_ID_LEN 2
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/*
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* 16-bit Subsystem Device ID assigned by the vendor. For further device
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* differentiation, as required. 0 if unused.
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*/
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_SUBSYS_DEVICE_ID_OFST 6
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_SUBSYS_DEVICE_ID_LEN 2
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/* 24-bit Device Class code, compliant with PCI-SIG Device Class codes */
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_DEVICE_CLASS_OFST 8
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_DEVICE_CLASS_LEN 3
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/* 8-bit vendor-assigned revision */
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_DEVICE_REVISION_OFST 11
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_DEVICE_REVISION_LEN 1
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/* Reserved (alignment) */
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_RESERVED_OFST 12
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_RESERVED_LEN 4
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/* MMIO region 0 base address (bus address), 0 if unused */
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_BASE_OFST 16
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_BASE_LEN 8
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_BASE_LO_OFST 16
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_BASE_LO_LEN 4
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_BASE_LO_LBN 128
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_BASE_LO_WIDTH 32
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_BASE_HI_OFST 20
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_BASE_HI_LEN 4
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_BASE_HI_LBN 160
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_BASE_HI_WIDTH 32
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/* MMIO region 0 size, 0 if unused */
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_SIZE_OFST 24
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_SIZE_LEN 8
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_SIZE_LO_OFST 24
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_SIZE_LO_LEN 4
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_SIZE_LO_LBN 192
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_SIZE_LO_WIDTH 32
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_SIZE_HI_OFST 28
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_SIZE_HI_LEN 4
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_SIZE_HI_LBN 224
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_SIZE_HI_WIDTH 32
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/* MMIO region 1 base address (bus address), 0 if unused */
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_BASE_OFST 32
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_BASE_LEN 8
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_BASE_LO_OFST 32
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_BASE_LO_LEN 4
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_BASE_LO_LBN 256
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_BASE_LO_WIDTH 32
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#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_BASE_HI_OFST 36
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_BASE_HI_LEN 4
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_BASE_HI_LBN 288
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_BASE_HI_WIDTH 32
|
|
/* MMIO region 1 size, 0 if unused */
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_SIZE_OFST 40
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_SIZE_LEN 8
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_SIZE_LO_OFST 40
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_SIZE_LO_LEN 4
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_SIZE_LO_LBN 320
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_SIZE_LO_WIDTH 32
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_SIZE_HI_OFST 44
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_SIZE_HI_LEN 4
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_SIZE_HI_LBN 352
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_SIZE_HI_WIDTH 32
|
|
/* MMIO region 2 base address (bus address), 0 if unused */
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_BASE_OFST 48
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_BASE_LEN 8
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_BASE_LO_OFST 48
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_BASE_LO_LEN 4
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_BASE_LO_LBN 384
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_BASE_LO_WIDTH 32
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_BASE_HI_OFST 52
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_BASE_HI_LEN 4
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_BASE_HI_LBN 416
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_BASE_HI_WIDTH 32
|
|
/* MMIO region 2 size, 0 if unused */
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_SIZE_OFST 56
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_SIZE_LEN 8
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_SIZE_LO_OFST 56
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_SIZE_LO_LEN 4
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_SIZE_LO_LBN 448
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_SIZE_LO_WIDTH 32
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_SIZE_HI_OFST 60
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_SIZE_HI_LEN 4
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_SIZE_HI_LBN 480
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_SIZE_HI_WIDTH 32
|
|
/* MMIO region 3 base address (bus address), 0 if unused */
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_BASE_OFST 64
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_BASE_LEN 8
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_BASE_LO_OFST 64
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_BASE_LO_LEN 4
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_BASE_LO_LBN 512
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_BASE_LO_WIDTH 32
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_BASE_HI_OFST 68
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_BASE_HI_LEN 4
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_BASE_HI_LBN 544
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_BASE_HI_WIDTH 32
|
|
/* MMIO region 3 size, 0 if unused */
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_SIZE_OFST 72
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_SIZE_LEN 8
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_SIZE_LO_OFST 72
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_SIZE_LO_LEN 4
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_SIZE_LO_LBN 576
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_SIZE_LO_WIDTH 32
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_SIZE_HI_OFST 76
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_SIZE_HI_LEN 4
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_SIZE_HI_LBN 608
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_SIZE_HI_WIDTH 32
|
|
/* MSI vector count */
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MSI_COUNT_OFST 80
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MSI_COUNT_LEN 4
|
|
/* Requester ID used by device (SMMU StreamID, GIC ITS DeviceID) */
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_REQUESTER_ID_OFST 84
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_REQUESTER_ID_LEN 4
|
|
|
|
/* MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_V2 msgresponse */
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_V2_LEN 92
|
|
/* Requester ID used by device for GIC ITS DeviceID */
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_V2_REQUESTER_DEVICE_ID_OFST 88
|
|
#define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_V2_REQUESTER_DEVICE_ID_LEN 4
|
|
|
|
/***********************************/
|
|
/*
|
|
* MC_CMD_CDX_BUS_DOWN
|
|
* Asserting reset on the CDX bus causes all devices on the bus to be quiesced.
|
|
* DMA bus mastering is disabled and any pending DMA request are flushed. Once
|
|
* the response is returned, the devices are guaranteed to no longer issue DMA
|
|
* requests or raise MSI interrupts. Further device MMIO accesses may have
|
|
* undefined results. While the bus reset is asserted, any of the enumeration
|
|
* or device configuration MCDIs will fail with EAGAIN. It is only legal to
|
|
* reload the relevant PL region containing CDX devices if the corresponding CDX
|
|
* bus is in reset. Depending on the implementation, the firmware may or may
|
|
* not enforce this restriction and it is up to the caller to make sure this
|
|
* requirement is satisfied.
|
|
*/
|
|
#define MC_CMD_CDX_BUS_DOWN 0x4
|
|
#define MC_CMD_CDX_BUS_DOWN_MSGSET 0x4
|
|
|
|
/* MC_CMD_CDX_BUS_DOWN_IN msgrequest */
|
|
#define MC_CMD_CDX_BUS_DOWN_IN_LEN 4
|
|
/* Bus number to put in reset, in range 0 to BUS_COUNT-1 */
|
|
#define MC_CMD_CDX_BUS_DOWN_IN_BUS_OFST 0
|
|
#define MC_CMD_CDX_BUS_DOWN_IN_BUS_LEN 4
|
|
|
|
/*
|
|
* MC_CMD_CDX_BUS_DOWN_OUT msgresponse: The bus is quiesced, no further
|
|
* upstream traffic for devices on this bus.
|
|
*/
|
|
#define MC_CMD_CDX_BUS_DOWN_OUT_LEN 0
|
|
|
|
/***********************************/
|
|
/*
|
|
* MC_CMD_CDX_BUS_UP
|
|
* After bus reset is de-asserted, devices are in a state which is functionally
|
|
* equivalent to each device having been reset with MC_CMD_CDX_DEVICE_RESET. In
|
|
* other words, device logic is reset in a hardware-specific way, MMIO accesses
|
|
* are forwarded to the device, DMA bus mastering is disabled and needs to be
|
|
* re-enabled with MC_CMD_CDX_DEVICE_DMA_ENABLE once the driver is ready to
|
|
* start servicing DMA. If the underlying number of devices or device resources
|
|
* changed (e.g. if PL was reloaded) while the bus was in reset, the bus driver
|
|
* is expected to re-enumerate the bus. Returns EALREADY if the bus was already
|
|
* up before the call.
|
|
*/
|
|
#define MC_CMD_CDX_BUS_UP 0x5
|
|
#define MC_CMD_CDX_BUS_UP_MSGSET 0x5
|
|
|
|
/* MC_CMD_CDX_BUS_UP_IN msgrequest */
|
|
#define MC_CMD_CDX_BUS_UP_IN_LEN 4
|
|
/* Bus number to take out of reset, in range 0 to BUS_COUNT-1 */
|
|
#define MC_CMD_CDX_BUS_UP_IN_BUS_OFST 0
|
|
#define MC_CMD_CDX_BUS_UP_IN_BUS_LEN 4
|
|
|
|
/* MC_CMD_CDX_BUS_UP_OUT msgresponse: The bus can now be enumerated. */
|
|
#define MC_CMD_CDX_BUS_UP_OUT_LEN 0
|
|
|
|
/***********************************/
|
|
/*
|
|
* MC_CMD_CDX_DEVICE_RESET
|
|
* After this call completes, device DMA and interrupts are quiesced, devices
|
|
* logic is reset in a hardware-specific way and DMA bus mastering is disabled.
|
|
*/
|
|
#define MC_CMD_CDX_DEVICE_RESET 0x6
|
|
#define MC_CMD_CDX_DEVICE_RESET_MSGSET 0x6
|
|
#undef MC_CMD_0x6_PRIVILEGE_CTG
|
|
|
|
#define MC_CMD_0x6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
|
|
|
|
/* MC_CMD_CDX_DEVICE_RESET_IN msgrequest */
|
|
#define MC_CMD_CDX_DEVICE_RESET_IN_LEN 8
|
|
/* Device bus number, in range 0 to BUS_COUNT-1 */
|
|
#define MC_CMD_CDX_DEVICE_RESET_IN_BUS_OFST 0
|
|
#define MC_CMD_CDX_DEVICE_RESET_IN_BUS_LEN 4
|
|
/* Device number relative to the bus, in range 0 to DEVICE_COUNT-1 for that bus */
|
|
#define MC_CMD_CDX_DEVICE_RESET_IN_DEVICE_OFST 4
|
|
#define MC_CMD_CDX_DEVICE_RESET_IN_DEVICE_LEN 4
|
|
|
|
/*
|
|
* MC_CMD_CDX_DEVICE_RESET_OUT msgresponse: The device is quiesced and all
|
|
* pending device initiated DMA has completed.
|
|
*/
|
|
#define MC_CMD_CDX_DEVICE_RESET_OUT_LEN 0
|
|
|
|
/***********************************/
|
|
/*
|
|
* MC_CMD_CDX_DEVICE_CONTROL_SET
|
|
* If BUS_MASTER is set to disabled, device DMA and interrupts are quiesced.
|
|
* Pending DMA requests and MSI interrupts are flushed and no further DMA or
|
|
* interrupts are issued after this command returns. If BUS_MASTER is set to
|
|
* enabled, device is allowed to initiate DMA. Whether interrupts are enabled
|
|
* also depends on the value of MSI_ENABLE bit. Note that, in this case, the
|
|
* device may start DMA before the host receives and processes the MCDI
|
|
* response. MSI_ENABLE masks or unmasks device interrupts only. Note that for
|
|
* interrupts to be delivered to the host, both BUS_MASTER and MSI_ENABLE needs
|
|
* to be set. MMIO_REGIONS_ENABLE enables or disables host accesses to device
|
|
* MMIO regions. Note that an implementation is allowed to permanently set this
|
|
* bit to 1, in which case MC_CMD_CDX_DEVICE_CONTROL_GET will always return 1
|
|
* for this bit, regardless of the value set here.
|
|
*/
|
|
#define MC_CMD_CDX_DEVICE_CONTROL_SET 0x7
|
|
#define MC_CMD_CDX_DEVICE_CONTROL_SET_MSGSET 0x7
|
|
#undef MC_CMD_0x7_PRIVILEGE_CTG
|
|
|
|
#define MC_CMD_0x7_PRIVILEGE_CTG SRIOV_CTG_ADMIN
|
|
|
|
/* MC_CMD_CDX_DEVICE_CONTROL_SET_IN msgrequest */
|
|
#define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_LEN 12
|
|
/* Device bus number, in range 0 to BUS_COUNT-1 */
|
|
#define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_BUS_OFST 0
|
|
#define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_BUS_LEN 4
|
|
/* Device number relative to the bus, in range 0 to DEVICE_COUNT-1 for that bus */
|
|
#define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_DEVICE_OFST 4
|
|
#define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_DEVICE_LEN 4
|
|
#define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_FLAGS_OFST 8
|
|
#define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_FLAGS_LEN 4
|
|
#define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_BUS_MASTER_ENABLE_OFST 8
|
|
#define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_BUS_MASTER_ENABLE_LBN 0
|
|
#define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_BUS_MASTER_ENABLE_WIDTH 1
|
|
#define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_MSI_ENABLE_OFST 8
|
|
#define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_MSI_ENABLE_LBN 1
|
|
#define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_MSI_ENABLE_WIDTH 1
|
|
#define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_MMIO_REGIONS_ENABLE_OFST 8
|
|
#define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_MMIO_REGIONS_ENABLE_LBN 2
|
|
#define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_MMIO_REGIONS_ENABLE_WIDTH 1
|
|
|
|
/* MC_CMD_CDX_DEVICE_CONTROL_SET_OUT msgresponse */
|
|
#define MC_CMD_CDX_DEVICE_CONTROL_SET_OUT_LEN 0
|
|
|
|
/***********************************/
|
|
/*
|
|
* MC_CMD_CDX_DEVICE_CONTROL_GET
|
|
* Returns device DMA, interrupt and MMIO region access control bits. See
|
|
* MC_CMD_CDX_DEVICE_CONTROL_SET for definition of the available control bits.
|
|
*/
|
|
#define MC_CMD_CDX_DEVICE_CONTROL_GET 0x8
|
|
#define MC_CMD_CDX_DEVICE_CONTROL_GET_MSGSET 0x8
|
|
#undef MC_CMD_0x8_PRIVILEGE_CTG
|
|
|
|
#define MC_CMD_0x8_PRIVILEGE_CTG SRIOV_CTG_ADMIN
|
|
|
|
/* MC_CMD_CDX_DEVICE_CONTROL_GET_IN msgrequest */
|
|
#define MC_CMD_CDX_DEVICE_CONTROL_GET_IN_LEN 8
|
|
/* Device bus number, in range 0 to BUS_COUNT-1 */
|
|
#define MC_CMD_CDX_DEVICE_CONTROL_GET_IN_BUS_OFST 0
|
|
#define MC_CMD_CDX_DEVICE_CONTROL_GET_IN_BUS_LEN 4
|
|
/* Device number relative to the bus, in range 0 to DEVICE_COUNT-1 for that bus */
|
|
#define MC_CMD_CDX_DEVICE_CONTROL_GET_IN_DEVICE_OFST 4
|
|
#define MC_CMD_CDX_DEVICE_CONTROL_GET_IN_DEVICE_LEN 4
|
|
|
|
/* MC_CMD_CDX_DEVICE_CONTROL_GET_OUT msgresponse */
|
|
#define MC_CMD_CDX_DEVICE_CONTROL_GET_OUT_LEN 4
|
|
#define MC_CMD_CDX_DEVICE_CONTROL_GET_OUT_FLAGS_OFST 0
|
|
#define MC_CMD_CDX_DEVICE_CONTROL_GET_OUT_FLAGS_LEN 4
|
|
#define MC_CMD_CDX_DEVICE_CONTROL_GET_OUT_BUS_MASTER_ENABLE_OFST 0
|
|
#define MC_CMD_CDX_DEVICE_CONTROL_GET_OUT_BUS_MASTER_ENABLE_LBN 0
|
|
#define MC_CMD_CDX_DEVICE_CONTROL_GET_OUT_BUS_MASTER_ENABLE_WIDTH 1
|
|
#define MC_CMD_CDX_DEVICE_CONTROL_GET_OUT_MSI_ENABLE_OFST 0
|
|
#define MC_CMD_CDX_DEVICE_CONTROL_GET_OUT_MSI_ENABLE_LBN 1
|
|
#define MC_CMD_CDX_DEVICE_CONTROL_GET_OUT_MSI_ENABLE_WIDTH 1
|
|
#define MC_CMD_CDX_DEVICE_CONTROL_GET_OUT_MMIO_REGIONS_ENABLE_OFST 0
|
|
#define MC_CMD_CDX_DEVICE_CONTROL_GET_OUT_MMIO_REGIONS_ENABLE_LBN 2
|
|
#define MC_CMD_CDX_DEVICE_CONTROL_GET_OUT_MMIO_REGIONS_ENABLE_WIDTH 1
|
|
|
|
/***********************************/
|
|
/*
|
|
* MC_CMD_CDX_DEVICE_WRITE_MSI_MSG
|
|
* Populates the MSI message to be used by the hardware to raise the specified
|
|
* interrupt vector. Versal-net implementation specific limitations are that
|
|
* only 4 CDX devices with MSI interrupt capability are supported and all
|
|
* vectors within a device must use the same write address. The command will
|
|
* return EINVAL if any of these limitations is violated.
|
|
*/
|
|
#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG 0x9
|
|
#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_MSGSET 0x9
|
|
#undef MC_CMD_0x9_PRIVILEGE_CTG
|
|
|
|
#define MC_CMD_0x9_PRIVILEGE_CTG SRIOV_CTG_ADMIN
|
|
|
|
/* MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN msgrequest */
|
|
#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_LEN 28
|
|
/* Device bus number, in range 0 to BUS_COUNT-1 */
|
|
#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_BUS_OFST 0
|
|
#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_BUS_LEN 4
|
|
/* Device number relative to the bus, in range 0 to DEVICE_COUNT-1 for that bus */
|
|
#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_DEVICE_OFST 4
|
|
#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_DEVICE_LEN 4
|
|
/*
|
|
* Device-relative MSI vector number. Must be < MSI_COUNT reported for the
|
|
* device.
|
|
*/
|
|
#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_VECTOR_OFST 8
|
|
#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_VECTOR_LEN 4
|
|
/* Reserved (alignment) */
|
|
#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_RESERVED_OFST 12
|
|
#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_RESERVED_LEN 4
|
|
/*
|
|
* MSI address to be used by the hardware. Typically, on ARM systems this
|
|
* address is translated by the IOMMU (if enabled) and it is the responsibility
|
|
* of the entity managing the IOMMU (APU kernel) to supply the correct IOVA
|
|
* here.
|
|
*/
|
|
#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_ADDRESS_OFST 16
|
|
#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_ADDRESS_LEN 8
|
|
#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_ADDRESS_LO_OFST 16
|
|
#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_ADDRESS_LO_LEN 4
|
|
#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_ADDRESS_LO_LBN 128
|
|
#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_ADDRESS_LO_WIDTH 32
|
|
#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_ADDRESS_HI_OFST 20
|
|
#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_ADDRESS_HI_LEN 4
|
|
#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_ADDRESS_HI_LBN 160
|
|
#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_ADDRESS_HI_WIDTH 32
|
|
/*
|
|
* MSI data to be used by the hardware. On versal-net, only the lower 16-bits
|
|
* are used, the remaining bits are ignored and should be set to zero.
|
|
*/
|
|
#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_DATA_OFST 24
|
|
#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_DATA_LEN 4
|
|
|
|
/* MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_OUT msgresponse */
|
|
#define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_OUT_LEN 0
|
|
|
|
/***********************************/
|
|
/* MC_CMD_V2_EXTN - Encapsulation for a v2 extended command */
|
|
#define MC_CMD_V2_EXTN 0x7f
|
|
|
|
/* MC_CMD_V2_EXTN_IN msgrequest */
|
|
#define MC_CMD_V2_EXTN_IN_LEN 4
|
|
/* the extended command number */
|
|
#define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0
|
|
#define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 15
|
|
#define MC_CMD_V2_EXTN_IN_UNUSED_LBN 15
|
|
#define MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1
|
|
/* the actual length of the encapsulated command */
|
|
#define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16
|
|
#define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10
|
|
#define MC_CMD_V2_EXTN_IN_UNUSED2_LBN 26
|
|
#define MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 2
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/* Type of command/response */
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#define MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_LBN 28
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#define MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_WIDTH 4
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/*
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* enum: MCDI command directed to versal-net. MCDI responses of this type
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* are not defined.
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*/
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#define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_PLATFORM 0x2
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#endif /* MC_CDX_PCOL_H */
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