181 lines
3.7 KiB
Plaintext
181 lines
3.7 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* sc7280 fragment for devices with Chrome bootloader
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*
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* This file mainly tries to abstract out the memory protections put into
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* place by the Chrome bootloader which are different than what's put into
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* place by Qualcomm's typical bootloader. It also has a smattering of other
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* things that will hold true for any conceivable Chrome design
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*
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* Copyright 2022 Google LLC.
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*/
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/*
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* Reserved memory changes
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*
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* Delete all unused memory nodes and define the peripheral memory regions
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* required by the setup for Chrome boards.
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*/
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/delete-node/ &cdsp_mem;
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/delete-node/ &domain_idle_states;
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/delete-node/ &gpu_zap_mem;
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/delete-node/ &gpu_zap_shader;
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/delete-node/ &hyp_mem;
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/delete-node/ &xbl_mem;
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/delete-node/ &reserved_xbl_uefi_log;
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/delete-node/ &sec_apps_mem;
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/ {
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cpus {
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domain_idle_states: domain-idle-states {
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CLUSTER_SLEEP_0: cluster-sleep-0 {
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compatible = "domain-idle-state";
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arm,psci-suspend-param = <0x40003444>;
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entry-latency-us = <2752>;
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exit-latency-us = <6562>;
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min-residency-us = <9926>;
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};
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};
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};
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reserved-memory {
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camera_mem: memory@8ad00000 {
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reg = <0x0 0x8ad00000 0x0 0x500000>;
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no-map;
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};
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venus_mem: memory@8b200000 {
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reg = <0x0 0x8b200000 0x0 0x500000>;
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no-map;
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};
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};
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};
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&CLUSTER_PD {
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domain-idle-states = <&CLUSTER_SLEEP_0>;
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};
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&lpass_aon {
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status = "okay";
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};
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&lpass_core {
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status = "okay";
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};
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&lpass_hm {
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status = "okay";
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};
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&lpasscc {
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status = "okay";
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};
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&pdc_reset {
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status = "okay";
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};
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/* The PMIC PON code isn't compatible w/ how Chrome EC/BIOS handle things. */
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&pmk8350_pon {
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status = "disabled";
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};
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/*
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* Chrome designs always boot from SPI flash hooked up to the qspi.
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*
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* It's expected that all boards will support "dual SPI" at 37.5 MHz.
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* If some boards need a different speed or have a package that allows
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* Quad SPI together with WP then those boards can easily override.
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*/
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&qspi {
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status = "okay";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>, <&qspi_data1>;
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pinctrl-1 = <&qspi_sleep>;
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spi_flash: flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <37500000>;
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spi-tx-bus-width = <2>;
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spi-rx-bus-width = <2>;
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};
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};
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/* Currently not used */
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&remoteproc_cdsp {
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/delete-property/ memory-region;
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};
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&remoteproc_wpss {
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compatible = "qcom,sc7280-wpss-pil";
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clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>,
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<&gcc GCC_WPSS_AHB_CLK>,
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<&gcc GCC_WPSS_RSCP_CLK>,
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<&rpmhcc RPMH_CXO_CLK>;
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clock-names = "ahb_bdg",
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"ahb",
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"rscp",
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"xo";
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resets = <&aoss_reset AOSS_CC_WCSS_RESTART>,
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<&pdc_reset PDC_WPSS_SYNC_RESET>;
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reset-names = "restart", "pdc_sync";
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qcom,halt-regs = <&tcsr_1 0x17000>;
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firmware-name = "ath11k/WCN6750/hw1.0/wpss.mdt";
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status = "okay";
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};
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&scm {
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/* TF-A firmware maps memory cached so mark dma-coherent to match. */
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dma-coherent;
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};
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&venus {
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iommus = <&apps_smmu 0x2180 0x20>,
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<&apps_smmu 0x2184 0x20>;
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status = "okay";
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video-firmware {
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iommus = <&apps_smmu 0x21a2 0x0>;
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};
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};
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&watchdog {
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status = "okay";
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};
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&wifi {
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status = "okay";
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wifi-firmware {
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iommus = <&apps_smmu 0x1c02 0x1>;
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};
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};
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/* PINCTRL - chrome-common pinctrl */
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&tlmm {
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qspi_sleep: qspi-sleep-state {
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pins = "gpio12", "gpio13", "gpio14", "gpio15";
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/*
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* When we're not actively transferring we want pins as GPIOs
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* with output disabled so that the quad SPI IP block stops
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* driving them. We rely on the normal pulls configured in
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* the active state and don't redefine them here. Also note
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* that we don't need the reverse (output-enable) in the
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* normal mode since the "output-enable" only matters for
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* GPIO function.
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*/
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function = "gpio";
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output-disable;
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};
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};
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