118 lines
3.0 KiB
Plaintext
118 lines
3.0 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2023 PHYTEC Messtechnik GmbH
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* Author: Wadim Egorov <w.egorov@phytec.de>, Christoph Stoidner <c.stoidner@phytec.de>
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* Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com>
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*
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* Product homepage:
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* phyBOARD-Segin carrier board is reused for the i.MX93 design.
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* https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6ul/
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*/
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/dts-v1/;
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#include "imx93-phycore-som.dtsi"
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/{
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model = "PHYTEC phyBOARD-Segin-i.MX93";
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compatible = "phytec,imx93-phyboard-segin", "phytec,imx93-phycore-som",
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"fsl,imx93";
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chosen {
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stdout-path = &lpuart1;
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};
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reg_usdhc2_vmmc: regulator-usdhc2 {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-name = "VCC_SD";
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};
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};
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/* Console */
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&lpuart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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/* eMMC */
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&usdhc1 {
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no-1-8-v;
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};
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/* SD-Card */
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&usdhc2 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2_default>, <&pinctrl_usdhc2_cd>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
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bus-width = <4>;
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cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
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no-mmc;
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no-sdio;
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vmmc-supply = <®_usdhc2_vmmc>;
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status = "okay";
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};
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&iomuxc {
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
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MX93_PAD_UART1_TXD__LPUART1_TX 0x30e
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>;
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};
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pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
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fsl,pins = <
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MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e
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>;
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};
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pinctrl_usdhc2_cd: usdhc2cdgrp {
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fsl,pins = <
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MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
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>;
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};
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pinctrl_usdhc2_default: usdhc2grp {
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fsl,pins = <
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MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e
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MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e
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MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
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MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
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MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
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MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e
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MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
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>;
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};
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pinctrl_usdhc2_100mhz: usdhc2grp {
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fsl,pins = <
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MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e
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MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e
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MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
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MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
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MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e
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MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e
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MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
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>;
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};
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pinctrl_usdhc2_200mhz: usdhc2grp {
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fsl,pins = <
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MX93_PAD_SD2_CLK__USDHC2_CLK 0x178e
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MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e
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MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x139e
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MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x139e
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MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e
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MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e
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MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
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>;
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};
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};
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