327 lines
6.4 KiB
Plaintext
327 lines
6.4 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2021 NXP
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*/
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/dts-v1/;
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#include "imx8ulp.dtsi"
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/ {
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model = "NXP i.MX8ULP EVK";
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compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp";
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chosen {
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stdout-path = &lpuart5;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0 0x80000000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0 0x28000000>;
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linux,cma-default;
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};
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m33_reserved: noncacheable-section@a8600000 {
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reg = <0 0xa8600000 0 0x1000000>;
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no-map;
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};
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rsc_table: rsc-table@1fff8000 {
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reg = <0 0x1fff8000 0 0x1000>;
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no-map;
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};
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vdev0vring0: vdev0vring0@aff00000 {
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reg = <0 0xaff00000 0 0x8000>;
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no-map;
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};
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vdev0vring1: vdev0vring1@aff08000 {
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reg = <0 0xaff08000 0 0x8000>;
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no-map;
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};
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vdev1vring0: vdev1vring0@aff10000 {
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reg = <0 0xaff10000 0 0x8000>;
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no-map;
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};
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vdev1vring1: vdev1vring1@aff18000 {
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reg = <0 0xaff18000 0 0x8000>;
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no-map;
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};
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vdevbuffer: vdevbuffer@a8400000 {
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compatible = "shared-dma-pool";
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reg = <0 0xa8400000 0 0x100000>;
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no-map;
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};
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};
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clock_ext_rmii: clock-ext-rmii {
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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clock-output-names = "ext_rmii_clk";
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#clock-cells = <0>;
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};
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clock_ext_ts: clock-ext-ts {
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compatible = "fixed-clock";
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/* External ts clock is 50MHZ from PHY on EVK board. */
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clock-frequency = <50000000>;
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clock-output-names = "ext_ts_clk";
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#clock-cells = <0>;
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};
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};
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&cm33 {
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mbox-names = "tx", "rx", "rxdb";
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mboxes = <&mu 0 1>,
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<&mu 1 1>,
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<&mu 3 1>;
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memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
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<&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
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status = "okay";
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};
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&flexspi2 {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_flexspi2_ptd>;
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pinctrl-1 = <&pinctrl_flexspi2_ptd>;
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status = "okay";
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mx25uw51345gxdi00: flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <200000000>;
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spi-tx-bus-width = <8>;
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spi-rx-bus-width = <8>;
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};
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};
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&lpuart5 {
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/* console */
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_lpuart5>;
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pinctrl-1 = <&pinctrl_lpuart5>;
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status = "okay";
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};
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&lpi2c7 {
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <400000>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_lpi2c7>;
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pinctrl-1 = <&pinctrl_lpi2c7>;
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status = "okay";
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ptn5150_1: typec@1d {
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compatible = "nxp,ptn5150";
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reg = <0x1d>;
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int-gpios = <&gpiof 3 IRQ_TYPE_EDGE_FALLING>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_typec1>;
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status = "disabled";
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};
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pcal6408: gpio@21 {
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compatible = "nxp,pcal9554b";
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reg = <0x21>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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ptn5150_2: typec@3d {
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compatible = "nxp,ptn5150";
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reg = <0x3d>;
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int-gpios = <&gpiof 5 IRQ_TYPE_EDGE_FALLING>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_typec2>;
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status = "disabled";
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};
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};
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&usbotg1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb1>;
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dr_mode = "otg";
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hnp-disable;
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srp-disable;
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adp-disable;
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over-current-active-low;
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status = "okay";
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};
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&usbphy1 {
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fsl,tx-d-cal = <110>;
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status = "okay";
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};
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&usbmisc1 {
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status = "okay";
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};
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&usbotg2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb2>;
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dr_mode = "otg";
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hnp-disable;
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srp-disable;
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adp-disable;
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over-current-active-low;
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status = "okay";
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};
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&usbphy2 {
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fsl,tx-d-cal = <110>;
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status = "okay";
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};
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&usbmisc2 {
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status = "okay";
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};
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&usdhc0 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
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pinctrl-0 = <&pinctrl_usdhc0>;
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pinctrl-1 = <&pinctrl_usdhc0>;
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pinctrl-2 = <&pinctrl_usdhc0>;
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pinctrl-3 = <&pinctrl_usdhc0>;
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non-removable;
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bus-width = <8>;
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status = "okay";
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};
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&fec {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_enet>;
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pinctrl-1 = <&pinctrl_enet>;
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clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
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<&pcc4 IMX8ULP_CLK_ENET>,
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<&cgc1 IMX8ULP_CLK_ENET_TS_SEL>,
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<&clock_ext_rmii>;
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clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
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assigned-clocks = <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>;
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assigned-clock-parents = <&clock_ext_ts>;
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phy-mode = "rmii";
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phy-handle = <ðphy>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy: ethernet-phy@1 {
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reg = <1>;
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micrel,led-mode = <1>;
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};
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};
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};
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&mu {
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status = "okay";
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};
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&iomuxc1 {
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pinctrl_enet: enetgrp {
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fsl,pins = <
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MX8ULP_PAD_PTE15__ENET0_MDC 0x43
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MX8ULP_PAD_PTE14__ENET0_MDIO 0x43
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MX8ULP_PAD_PTE17__ENET0_RXER 0x43
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MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43
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MX8ULP_PAD_PTF1__ENET0_RXD0 0x43
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MX8ULP_PAD_PTE20__ENET0_RXD1 0x43
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MX8ULP_PAD_PTE16__ENET0_TXEN 0x43
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MX8ULP_PAD_PTE23__ENET0_TXD0 0x43
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MX8ULP_PAD_PTE22__ENET0_TXD1 0x43
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MX8ULP_PAD_PTE19__ENET0_REFCLK 0x43
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MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43
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>;
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};
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pinctrl_flexspi2_ptd: flexspi2ptdgrp {
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fsl,pins = <
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MX8ULP_PAD_PTD12__FLEXSPI2_A_SS0_B 0x42
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MX8ULP_PAD_PTD13__FLEXSPI2_A_SCLK 0x42
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MX8ULP_PAD_PTD14__FLEXSPI2_A_DATA3 0x42
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MX8ULP_PAD_PTD15__FLEXSPI2_A_DATA2 0x42
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MX8ULP_PAD_PTD16__FLEXSPI2_A_DATA1 0x42
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MX8ULP_PAD_PTD17__FLEXSPI2_A_DATA0 0x42
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MX8ULP_PAD_PTD18__FLEXSPI2_A_DQS 0x42
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MX8ULP_PAD_PTD19__FLEXSPI2_A_DATA7 0x42
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MX8ULP_PAD_PTD20__FLEXSPI2_A_DATA6 0x42
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MX8ULP_PAD_PTD21__FLEXSPI2_A_DATA5 0x42
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MX8ULP_PAD_PTD22__FLEXSPI2_A_DATA4 0x42
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>;
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};
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pinctrl_lpuart5: lpuart5grp {
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fsl,pins = <
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MX8ULP_PAD_PTF14__LPUART5_TX 0x3
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MX8ULP_PAD_PTF15__LPUART5_RX 0x3
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>;
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};
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pinctrl_lpi2c7: lpi2c7grp {
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fsl,pins = <
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MX8ULP_PAD_PTE12__LPI2C7_SCL 0x20
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MX8ULP_PAD_PTE13__LPI2C7_SDA 0x20
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>;
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};
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pinctrl_typec1: typec1grp {
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fsl,pins = <
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MX8ULP_PAD_PTF3__PTF3 0x3
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>;
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};
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pinctrl_typec2: typec2grp {
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fsl,pins = <
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MX8ULP_PAD_PTF5__PTF5 0x3
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>;
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};
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pinctrl_usb1: usb1grp {
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fsl,pins = <
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MX8ULP_PAD_PTF2__USB0_ID 0x10003
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MX8ULP_PAD_PTF4__USB0_OC 0x10003
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>;
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};
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pinctrl_usb2: usb2grp {
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fsl,pins = <
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MX8ULP_PAD_PTD23__USB1_ID 0x10003
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MX8ULP_PAD_PTF6__USB1_OC 0x10003
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>;
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};
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pinctrl_usdhc0: usdhc0grp {
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fsl,pins = <
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MX8ULP_PAD_PTD1__SDHC0_CMD 0x3
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MX8ULP_PAD_PTD2__SDHC0_CLK 0x10002
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MX8ULP_PAD_PTD10__SDHC0_D0 0x3
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MX8ULP_PAD_PTD9__SDHC0_D1 0x3
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MX8ULP_PAD_PTD8__SDHC0_D2 0x3
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MX8ULP_PAD_PTD7__SDHC0_D3 0x3
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MX8ULP_PAD_PTD6__SDHC0_D4 0x3
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MX8ULP_PAD_PTD5__SDHC0_D5 0x3
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MX8ULP_PAD_PTD4__SDHC0_D6 0x3
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MX8ULP_PAD_PTD3__SDHC0_D7 0x3
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MX8ULP_PAD_PTD11__SDHC0_DQS 0x10002
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>;
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};
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};
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