115 lines
3.4 KiB
Plaintext
115 lines
3.4 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only and MIT
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/*
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* Copyright 2024 NXP
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*/
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lvds1_subsys: bus@57240000 {
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compatible = "simple-bus";
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interrupt-parent = <&irqsteer_lvds1>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x57240000 0x0 0x57240000 0x10000>;
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irqsteer_lvds1: interrupt-controller@57240000 {
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compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
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reg = <0x57240000 0x1000>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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interrupt-parent = <&gic>;
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#interrupt-cells = <1>;
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clocks = <&lvds1_lis_lpcg IMX_LPCG_CLK_4>;
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clock-names = "ipg";
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power-domains = <&pd IMX_SC_R_LVDS_1>;
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fsl,channel = <0>;
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fsl,num-irqs = <32>;
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};
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lvds1_lis_lpcg: clock-controller@57243000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x57243000 0x4>;
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#clock-cells = <1>;
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clocks = <&lvds_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_4>;
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clock-output-names = "lvds1_lis_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_LVDS_1>;
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};
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lvds1_pwm_lpcg: clock-controller@5724300c {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5724300c 0x4>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>,
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<&lvds_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
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clock-output-names = "lvds1_pwm_lpcg_clk",
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"lvds1_pwm_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>;
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};
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lvds1_i2c0_lpcg: clock-controller@57243010 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x57243010 0x4>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>,
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<&lvds_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
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clock-output-names = "lvds1_i2c0_lpcg_clk",
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"lvds1_i2c0_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
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};
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lvds1_i2c1_lpcg: clock-controller@57243014 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x57243014 0x4>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>,
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<&lvds_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
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clock-output-names = "lvds1_i2c1_lpcg_clk",
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"lvds1_i2c1_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
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};
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pwm_lvds1: pwm@57244000 {
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compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
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reg = <0x57244000 0x1000>;
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clocks = <&lvds1_pwm_lpcg IMX_LPCG_CLK_4>,
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<&lvds1_pwm_lpcg IMX_LPCG_CLK_0>;
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clock-names = "ipg", "per";
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assigned-clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>;
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assigned-clock-rates = <24000000>;
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#pwm-cells = <3>;
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power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>;
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status = "disabled";
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};
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i2c0_lvds1: i2c@57246000 {
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compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
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reg = <0x57246000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <8>;
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clocks = <&lvds1_i2c0_lpcg IMX_LPCG_CLK_0>,
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<&lvds1_i2c0_lpcg IMX_LPCG_CLK_4>;
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clock-names = "per", "ipg";
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assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>;
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assigned-clock-rates = <24000000>;
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power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
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status = "disabled";
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};
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i2c1_lvds1: i2c@57247000 {
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compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
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reg = <0x57247000 0x1000>;
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interrupts = <9>;
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clocks = <&lvds1_i2c1_lpcg IMX_LPCG_CLK_0>,
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<&lvds1_i2c1_lpcg IMX_LPCG_CLK_4>;
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clock-names = "per", "ipg";
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assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>;
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assigned-clock-rates = <24000000>;
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power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
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status = "disabled";
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};
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};
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