388 lines
11 KiB
Plaintext
388 lines
11 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018-2020 NXP
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* Dong Aisheng <aisheng.dong@nxp.com>
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*/
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#include <dt-bindings/clock/imx8-lpcg.h>
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#include <dt-bindings/firmware/imx/rsrc.h>
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lsio_bus_clk: clock-lsio-bus {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "lsio_bus_clk";
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};
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lsio_subsys: bus@5d000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x5d000000 0x0 0x5d000000 0x1000000>,
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<0x08000000 0x0 0x08000000 0x10000000>;
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lsio_pwm0: pwm@5d000000 {
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compatible = "fsl,imx27-pwm";
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reg = <0x5d000000 0x10000>;
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clock-names = "ipg", "per";
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clocks = <&pwm0_lpcg IMX_LPCG_CLK_6>,
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<&pwm0_lpcg IMX_LPCG_CLK_1>;
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assigned-clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;
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assigned-clock-rates = <24000000>;
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#pwm-cells = <3>;
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interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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lsio_pwm1: pwm@5d010000 {
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compatible = "fsl,imx27-pwm";
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reg = <0x5d010000 0x10000>;
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clock-names = "ipg", "per";
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clocks = <&pwm1_lpcg IMX_LPCG_CLK_6>,
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<&pwm1_lpcg IMX_LPCG_CLK_1>;
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assigned-clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>;
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assigned-clock-rates = <24000000>;
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#pwm-cells = <3>;
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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lsio_pwm2: pwm@5d020000 {
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compatible = "fsl,imx27-pwm";
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reg = <0x5d020000 0x10000>;
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clock-names = "ipg", "per";
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clocks = <&pwm2_lpcg IMX_LPCG_CLK_6>,
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<&pwm2_lpcg IMX_LPCG_CLK_1>;
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assigned-clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>;
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assigned-clock-rates = <24000000>;
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#pwm-cells = <3>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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lsio_pwm3: pwm@5d030000 {
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compatible = "fsl,imx27-pwm";
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reg = <0x5d030000 0x10000>;
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clock-names = "ipg", "per";
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clocks = <&pwm3_lpcg IMX_LPCG_CLK_6>,
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<&pwm3_lpcg IMX_LPCG_CLK_1>;
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assigned-clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>;
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assigned-clock-rates = <24000000>;
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#pwm-cells = <3>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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lsio_gpio0: gpio@5d080000 {
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reg = <0x5d080000 0x10000>;
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interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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power-domains = <&pd IMX_SC_R_GPIO_0>;
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};
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lsio_gpio1: gpio@5d090000 {
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reg = <0x5d090000 0x10000>;
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interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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power-domains = <&pd IMX_SC_R_GPIO_1>;
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};
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lsio_gpio2: gpio@5d0a0000 {
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reg = <0x5d0a0000 0x10000>;
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interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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power-domains = <&pd IMX_SC_R_GPIO_2>;
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};
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lsio_gpio3: gpio@5d0b0000 {
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reg = <0x5d0b0000 0x10000>;
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interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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power-domains = <&pd IMX_SC_R_GPIO_3>;
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};
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lsio_gpio4: gpio@5d0c0000 {
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reg = <0x5d0c0000 0x10000>;
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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power-domains = <&pd IMX_SC_R_GPIO_4>;
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};
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lsio_gpio5: gpio@5d0d0000 {
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reg = <0x5d0d0000 0x10000>;
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interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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power-domains = <&pd IMX_SC_R_GPIO_5>;
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};
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lsio_gpio6: gpio@5d0e0000 {
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reg = <0x5d0e0000 0x10000>;
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interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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power-domains = <&pd IMX_SC_R_GPIO_6>;
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};
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lsio_gpio7: gpio@5d0f0000 {
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reg = <0x5d0f0000 0x10000>;
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interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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power-domains = <&pd IMX_SC_R_GPIO_7>;
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};
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flexspi0: spi@5d120000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nxp,imx8qxp-fspi";
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reg = <0x5d120000 0x10000>, <0x08000000 0x10000000>;
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reg-names = "fspi_base", "fspi_mmap";
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interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>,
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<&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>;
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clock-names = "fspi_en", "fspi";
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power-domains = <&pd IMX_SC_R_FSPI_0>;
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status = "disabled";
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};
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lsio_mu0: mailbox@5d1b0000 {
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reg = <0x5d1b0000 0x10000>;
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interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <2>;
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status = "disabled";
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};
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lsio_mu1: mailbox@5d1c0000 {
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reg = <0x5d1c0000 0x10000>;
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interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <2>;
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};
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lsio_mu2: mailbox@5d1d0000 {
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reg = <0x5d1d0000 0x10000>;
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interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <2>;
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status = "disabled";
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};
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lsio_mu3: mailbox@5d1e0000 {
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reg = <0x5d1e0000 0x10000>;
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interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <2>;
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status = "disabled";
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};
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lsio_mu4: mailbox@5d1f0000 {
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reg = <0x5d1f0000 0x10000>;
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interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <2>;
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status = "disabled";
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};
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lsio_mu5: mailbox@5d200000 {
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reg = <0x5d200000 0x10000>;
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interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <2>;
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power-domains = <&pd IMX_SC_R_MU_5A>;
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status = "disabled";
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};
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lsio_mu6: mailbox@5d210000 {
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reg = <0x5d210000 0x10000>;
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interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <2>;
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power-domains = <&pd IMX_SC_R_MU_6A>;
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status = "disabled";
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};
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lsio_mu13: mailbox@5d280000 {
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reg = <0x5d280000 0x10000>;
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interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <2>;
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power-domains = <&pd IMX_SC_R_MU_13A>;
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};
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/* LPCG clocks */
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pwm0_lpcg: clock-controller@5d400000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5d400000 0x10000>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
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<&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
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<&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
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<&lsio_bus_clk>,
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<&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
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<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
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<IMX_LPCG_CLK_6>;
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clock-output-names = "pwm0_lpcg_ipg_clk",
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"pwm0_lpcg_ipg_hf_clk",
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"pwm0_lpcg_ipg_s_clk",
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"pwm0_lpcg_ipg_slv_clk",
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"pwm0_lpcg_ipg_mstr_clk";
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power-domains = <&pd IMX_SC_R_PWM_0>;
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};
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pwm1_lpcg: clock-controller@5d410000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5d410000 0x10000>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
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<&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
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<&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
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<&lsio_bus_clk>,
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<&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
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<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
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<IMX_LPCG_CLK_6>;
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clock-output-names = "pwm1_lpcg_ipg_clk",
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"pwm1_lpcg_ipg_hf_clk",
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"pwm1_lpcg_ipg_s_clk",
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"pwm1_lpcg_ipg_slv_clk",
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"pwm1_lpcg_ipg_mstr_clk";
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power-domains = <&pd IMX_SC_R_PWM_1>;
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};
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pwm2_lpcg: clock-controller@5d420000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5d420000 0x10000>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
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<&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
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<&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
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<&lsio_bus_clk>,
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<&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
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<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
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<IMX_LPCG_CLK_6>;
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clock-output-names = "pwm2_lpcg_ipg_clk",
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"pwm2_lpcg_ipg_hf_clk",
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"pwm2_lpcg_ipg_s_clk",
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"pwm2_lpcg_ipg_slv_clk",
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"pwm2_lpcg_ipg_mstr_clk";
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power-domains = <&pd IMX_SC_R_PWM_2>;
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};
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pwm3_lpcg: clock-controller@5d430000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5d430000 0x10000>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
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<&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
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<&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
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<&lsio_bus_clk>,
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<&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
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<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
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<IMX_LPCG_CLK_6>;
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clock-output-names = "pwm3_lpcg_ipg_clk",
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"pwm3_lpcg_ipg_hf_clk",
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"pwm3_lpcg_ipg_s_clk",
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"pwm3_lpcg_ipg_slv_clk",
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"pwm3_lpcg_ipg_mstr_clk";
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power-domains = <&pd IMX_SC_R_PWM_3>;
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};
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pwm4_lpcg: clock-controller@5d440000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5d440000 0x10000>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
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<&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
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<&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
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<&lsio_bus_clk>,
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<&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
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<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
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<IMX_LPCG_CLK_6>;
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clock-output-names = "pwm4_lpcg_ipg_clk",
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"pwm4_lpcg_ipg_hf_clk",
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"pwm4_lpcg_ipg_s_clk",
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"pwm4_lpcg_ipg_slv_clk",
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"pwm4_lpcg_ipg_mstr_clk";
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power-domains = <&pd IMX_SC_R_PWM_4>;
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};
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pwm5_lpcg: clock-controller@5d450000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5d450000 0x10000>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
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<&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
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<&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
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<&lsio_bus_clk>,
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<&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
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<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
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<IMX_LPCG_CLK_6>;
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clock-output-names = "pwm5_lpcg_ipg_clk",
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"pwm5_lpcg_ipg_hf_clk",
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"pwm5_lpcg_ipg_s_clk",
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"pwm5_lpcg_ipg_slv_clk",
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"pwm5_lpcg_ipg_mstr_clk";
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power-domains = <&pd IMX_SC_R_PWM_5>;
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};
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pwm6_lpcg: clock-controller@5d460000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5d460000 0x10000>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
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<&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
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<&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
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<&lsio_bus_clk>,
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<&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
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<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
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<IMX_LPCG_CLK_6>;
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clock-output-names = "pwm6_lpcg_ipg_clk",
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"pwm6_lpcg_ipg_hf_clk",
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"pwm6_lpcg_ipg_s_clk",
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"pwm6_lpcg_ipg_slv_clk",
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"pwm6_lpcg_ipg_mstr_clk";
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power-domains = <&pd IMX_SC_R_PWM_6>;
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};
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pwm7_lpcg: clock-controller@5d470000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5d470000 0x10000>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
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<&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
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<&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
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<&lsio_bus_clk>,
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<&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
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<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
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<IMX_LPCG_CLK_6>;
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clock-output-names = "pwm7_lpcg_ipg_clk",
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"pwm7_lpcg_ipg_hf_clk",
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"pwm7_lpcg_ipg_s_clk",
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"pwm7_lpcg_ipg_slv_clk",
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"pwm7_lpcg_ipg_mstr_clk";
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power-domains = <&pd IMX_SC_R_PWM_7>;
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};
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};
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