151 lines
4.1 KiB
C
151 lines
4.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#ifndef _ASM_X86_CPU_ENTRY_AREA_H
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#define _ASM_X86_CPU_ENTRY_AREA_H
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#include <linux/percpu-defs.h>
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#include <asm/processor.h>
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#include <asm/intel_ds.h>
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#ifdef CONFIG_X86_64
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#ifdef CONFIG_AMD_MEM_ENCRYPT
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#define VC_EXCEPTION_STKSZ EXCEPTION_STKSZ
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#else
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#define VC_EXCEPTION_STKSZ 0
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#endif
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/* Macro to enforce the same ordering and stack sizes */
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#define ESTACKS_MEMBERS(guardsize, optional_stack_size) \
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char DF_stack_guard[guardsize]; \
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char DF_stack[EXCEPTION_STKSZ]; \
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char NMI_stack_guard[guardsize]; \
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char NMI_stack[EXCEPTION_STKSZ]; \
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char DB_stack_guard[guardsize]; \
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char DB_stack[EXCEPTION_STKSZ]; \
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char MCE_stack_guard[guardsize]; \
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char MCE_stack[EXCEPTION_STKSZ]; \
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char VC_stack_guard[guardsize]; \
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char VC_stack[optional_stack_size]; \
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char VC2_stack_guard[guardsize]; \
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char VC2_stack[optional_stack_size]; \
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char IST_top_guard[guardsize]; \
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/* The exception stacks' physical storage. No guard pages required */
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struct exception_stacks {
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ESTACKS_MEMBERS(0, VC_EXCEPTION_STKSZ)
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};
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/* The effective cpu entry area mapping with guard pages. */
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struct cea_exception_stacks {
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ESTACKS_MEMBERS(PAGE_SIZE, EXCEPTION_STKSZ)
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};
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/*
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* The exception stack ordering in [cea_]exception_stacks
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*/
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enum exception_stack_ordering {
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ESTACK_DF,
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ESTACK_NMI,
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ESTACK_DB,
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ESTACK_MCE,
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ESTACK_VC,
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ESTACK_VC2,
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N_EXCEPTION_STACKS
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};
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#define CEA_ESTACK_SIZE(st) \
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sizeof(((struct cea_exception_stacks *)0)->st## _stack)
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#define CEA_ESTACK_BOT(ceastp, st) \
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((unsigned long)&(ceastp)->st## _stack)
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#define CEA_ESTACK_TOP(ceastp, st) \
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(CEA_ESTACK_BOT(ceastp, st) + CEA_ESTACK_SIZE(st))
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#define CEA_ESTACK_OFFS(st) \
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offsetof(struct cea_exception_stacks, st## _stack)
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#define CEA_ESTACK_PAGES \
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(sizeof(struct cea_exception_stacks) / PAGE_SIZE)
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#endif
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/*
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* cpu_entry_area is a percpu region that contains things needed by the CPU
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* and early entry/exit code. Real types aren't used for all fields here
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* to avoid circular header dependencies.
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*
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* Every field is a virtual alias of some other allocated backing store.
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* There is no direct allocation of a struct cpu_entry_area.
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*/
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struct cpu_entry_area {
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char gdt[PAGE_SIZE];
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/*
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* The GDT is just below entry_stack and thus serves (on x86_64) as
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* a a read-only guard page.
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*/
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struct entry_stack_page entry_stack_page;
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/*
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* On x86_64, the TSS is mapped RO. On x86_32, it's mapped RW because
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* we need task switches to work, and task switches write to the TSS.
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*/
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struct tss_struct tss;
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#ifdef CONFIG_X86_64
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/*
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* Exception stacks used for IST entries with guard pages.
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*/
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struct cea_exception_stacks estacks;
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#endif
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/*
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* Per CPU debug store for Intel performance monitoring. Wastes a
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* full page at the moment.
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*/
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struct debug_store cpu_debug_store;
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/*
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* The actual PEBS/BTS buffers must be mapped to user space
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* Reserve enough fixmap PTEs.
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*/
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struct debug_store_buffers cpu_debug_buffers;
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};
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#define CPU_ENTRY_AREA_SIZE (sizeof(struct cpu_entry_area))
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DECLARE_PER_CPU(struct cpu_entry_area *, cpu_entry_area);
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DECLARE_PER_CPU(struct cea_exception_stacks *, cea_exception_stacks);
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extern void setup_cpu_entry_areas(void);
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extern void cea_set_pte(void *cea_vaddr, phys_addr_t pa, pgprot_t flags);
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/* Single page reserved for the readonly IDT mapping: */
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#define CPU_ENTRY_AREA_RO_IDT CPU_ENTRY_AREA_BASE
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#define CPU_ENTRY_AREA_PER_CPU (CPU_ENTRY_AREA_RO_IDT + PAGE_SIZE)
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#define CPU_ENTRY_AREA_RO_IDT_VADDR ((void *)CPU_ENTRY_AREA_RO_IDT)
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#ifdef CONFIG_X86_32
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#define CPU_ENTRY_AREA_MAP_SIZE (CPU_ENTRY_AREA_PER_CPU + \
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(CPU_ENTRY_AREA_SIZE * NR_CPUS) - \
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CPU_ENTRY_AREA_BASE)
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#else
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#define CPU_ENTRY_AREA_MAP_SIZE P4D_SIZE
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#endif
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extern struct cpu_entry_area *get_cpu_entry_area(int cpu);
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static inline struct entry_stack *cpu_entry_stack(int cpu)
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{
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return &get_cpu_entry_area(cpu)->entry_stack_page.stack;
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}
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#define __this_cpu_ist_top_va(name) \
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CEA_ESTACK_TOP(__this_cpu_read(cea_exception_stacks), name)
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#define __this_cpu_ist_bottom_va(name) \
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CEA_ESTACK_BOT(__this_cpu_read(cea_exception_stacks), name)
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#endif
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