1242 lines
34 KiB
Plaintext
1242 lines
34 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* dts file for Xilinx ZynqMP
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*
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* (C) Copyright 2014 - 2021, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@amd.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/power/xlnx-zynqmp-power.h>
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#include <dt-bindings/reset/xlnx-zynqmp-resets.h>
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/ {
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compatible = "xlnx,zynqmp";
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#address-cells = <2>;
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#size-cells = <2>;
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options {
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u-boot {
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compatible = "u-boot,config";
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bootscr-address = /bits/ 64 <0x20000000>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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enable-method = "psci";
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operating-points-v2 = <&cpu_opp_table>;
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reg = <0x0>;
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cpu-idle-states = <&CPU_SLEEP_0>;
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next-level-cache = <&L2>;
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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enable-method = "psci";
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reg = <0x1>;
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operating-points-v2 = <&cpu_opp_table>;
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cpu-idle-states = <&CPU_SLEEP_0>;
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next-level-cache = <&L2>;
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};
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cpu2: cpu@2 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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enable-method = "psci";
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reg = <0x2>;
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operating-points-v2 = <&cpu_opp_table>;
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cpu-idle-states = <&CPU_SLEEP_0>;
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next-level-cache = <&L2>;
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};
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cpu3: cpu@3 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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enable-method = "psci";
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reg = <0x3>;
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operating-points-v2 = <&cpu_opp_table>;
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cpu-idle-states = <&CPU_SLEEP_0>;
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next-level-cache = <&L2>;
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};
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L2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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};
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idle-states {
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entry-method = "psci";
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CPU_SLEEP_0: cpu-sleep-0 {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x40000000>;
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local-timer-stop;
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entry-latency-us = <300>;
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exit-latency-us = <600>;
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min-residency-us = <10000>;
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};
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};
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};
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cpu_opp_table: opp-table-cpu {
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compatible = "operating-points-v2";
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opp-shared;
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opp00 {
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opp-hz = /bits/ 64 <1199999988>;
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opp-microvolt = <1000000>;
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clock-latency-ns = <500000>;
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};
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opp01 {
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opp-hz = /bits/ 64 <599999994>;
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opp-microvolt = <1000000>;
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clock-latency-ns = <500000>;
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};
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opp02 {
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opp-hz = /bits/ 64 <399999996>;
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opp-microvolt = <1000000>;
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clock-latency-ns = <500000>;
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};
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opp03 {
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opp-hz = /bits/ 64 <299999997>;
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opp-microvolt = <1000000>;
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clock-latency-ns = <500000>;
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};
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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rproc_0_fw_image: memory@3ed00000 {
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no-map;
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reg = <0x0 0x3ed00000 0x0 0x40000>;
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};
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rproc_1_fw_image: memory@3ef00000 {
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no-map;
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reg = <0x0 0x3ef00000 0x0 0x40000>;
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};
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};
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zynqmp_ipi: zynqmp-ipi {
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bootph-all;
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compatible = "xlnx,zynqmp-ipi-mailbox";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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xlnx,ipi-id = <0>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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ipi_mailbox_pmu1: mailbox@ff9905c0 {
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bootph-all;
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compatible = "xlnx,zynqmp-ipi-dest-mailbox";
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reg = <0x0 0xff9905c0 0x0 0x20>,
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<0x0 0xff9905e0 0x0 0x20>,
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<0x0 0xff990e80 0x0 0x20>,
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<0x0 0xff990ea0 0x0 0x20>;
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reg-names = "local_request_region",
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"local_response_region",
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"remote_request_region",
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"remote_response_region";
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#mbox-cells = <1>;
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xlnx,ipi-id = <4>;
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};
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};
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dcc: dcc {
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compatible = "arm,dcc";
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status = "disabled";
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bootph-all;
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};
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pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>,
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<&cpu1>,
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<&cpu2>,
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<&cpu3>;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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firmware {
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optee: optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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zynqmp_firmware: zynqmp-firmware {
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compatible = "xlnx,zynqmp-firmware";
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#power-domain-cells = <1>;
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method = "smc";
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bootph-all;
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zynqmp_power: power-management {
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bootph-all;
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compatible = "xlnx,zynqmp-power";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>;
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mbox-names = "tx", "rx";
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};
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soc-nvmem {
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compatible = "xlnx,zynqmp-nvmem-fw";
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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soc_revision: soc-revision@0 {
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reg = <0x0 0x4>;
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};
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/* efuse access */
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efuse_dna: efuse-dna@c {
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reg = <0xc 0xc>;
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};
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efuse_usr0: efuse-usr0@20 {
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reg = <0x20 0x4>;
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};
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efuse_usr1: efuse-usr1@24 {
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reg = <0x24 0x4>;
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};
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efuse_usr2: efuse-usr2@28 {
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reg = <0x28 0x4>;
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};
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efuse_usr3: efuse-usr3@2c {
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reg = <0x2c 0x4>;
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};
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efuse_usr4: efuse-usr4@30 {
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reg = <0x30 0x4>;
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};
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efuse_usr5: efuse-usr5@34 {
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reg = <0x34 0x4>;
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};
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efuse_usr6: efuse-usr6@38 {
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reg = <0x38 0x4>;
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};
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efuse_usr7: efuse-usr7@3c {
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reg = <0x3c 0x4>;
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};
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efuse_miscusr: efuse-miscusr@40 {
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reg = <0x40 0x4>;
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};
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efuse_chash: efuse-chash@50 {
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reg = <0x50 0x4>;
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};
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efuse_pufmisc: efuse-pufmisc@54 {
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reg = <0x54 0x4>;
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};
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efuse_sec: efuse-sec@58 {
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reg = <0x58 0x4>;
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};
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efuse_spkid: efuse-spkid@5c {
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reg = <0x5c 0x4>;
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};
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efuse_aeskey: efuse-aeskey@60 {
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reg = <0x60 0x20>;
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};
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efuse_ppk0hash: efuse-ppk0hash@a0 {
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reg = <0xa0 0x30>;
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};
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efuse_ppk1hash: efuse-ppk1hash@d0 {
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reg = <0xd0 0x30>;
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};
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efuse_pufuser: efuse-pufuser@100 {
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reg = <0x100 0x7F>;
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};
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};
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};
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zynqmp_pcap: pcap {
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compatible = "xlnx,zynqmp-pcap-fpga";
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};
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xlnx_aes: zynqmp-aes {
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compatible = "xlnx,zynqmp-aes";
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};
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zynqmp_reset: reset-controller {
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compatible = "xlnx,zynqmp-reset";
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#reset-cells = <1>;
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};
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pinctrl0: pinctrl {
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compatible = "xlnx,zynqmp-pinctrl";
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status = "disabled";
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};
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modepin_gpio: gpio {
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compatible = "xlnx,zynqmp-gpio-modepin";
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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fpga_full: fpga-region {
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compatible = "fpga-region";
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fpga-mgr = <&zynqmp_pcap>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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};
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rproc_lockstep: remoteproc@ffe00000 {
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compatible = "xlnx,zynqmp-r5fss";
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xlnx,cluster-mode = <1>;
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xlnx,tcm-mode = <1>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>,
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<0x0 0x20000 0x0 0xffe20000 0x0 0x10000>,
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<0x0 0x10000 0x0 0xffe10000 0x0 0x10000>,
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<0x0 0x30000 0x0 0xffe30000 0x0 0x10000>;
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r5f@0 {
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compatible = "xlnx,zynqmp-r5f";
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reg = <0x0 0x0 0x0 0x10000>,
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<0x0 0x20000 0x0 0x10000>,
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<0x0 0x10000 0x0 0x10000>,
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<0x0 0x30000 0x0 0x10000>;
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reg-names = "atcm0", "btcm0", "atcm1", "btcm1";
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power-domains = <&zynqmp_firmware PD_RPU_0>,
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<&zynqmp_firmware PD_R5_0_ATCM>,
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<&zynqmp_firmware PD_R5_0_BTCM>,
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<&zynqmp_firmware PD_R5_1_ATCM>,
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<&zynqmp_firmware PD_R5_1_BTCM>;
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memory-region = <&rproc_0_fw_image>;
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};
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r5f@1 {
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compatible = "xlnx,zynqmp-r5f";
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reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>;
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reg-names = "atcm0", "btcm0";
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power-domains = <&zynqmp_firmware PD_RPU_1>,
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<&zynqmp_firmware PD_R5_1_ATCM>,
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<&zynqmp_firmware PD_R5_1_BTCM>;
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memory-region = <&rproc_1_fw_image>;
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};
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};
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rproc_split: remoteproc-split@ffe00000 {
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status = "disabled";
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compatible = "xlnx,zynqmp-r5fss";
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xlnx,cluster-mode = <0>;
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xlnx,tcm-mode = <0>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>,
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<0x0 0x20000 0x0 0xffe20000 0x0 0x10000>,
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<0x1 0x0 0x0 0xffe90000 0x0 0x10000>,
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<0x1 0x20000 0x0 0xffeb0000 0x0 0x10000>;
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r5f@0 {
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compatible = "xlnx,zynqmp-r5f";
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reg = <0x0 0x0 0x0 0x10000>, <0x0 0x20000 0x0 0x10000>;
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reg-names = "atcm0", "btcm0";
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power-domains = <&zynqmp_firmware PD_RPU_0>,
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<&zynqmp_firmware PD_R5_0_ATCM>,
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<&zynqmp_firmware PD_R5_0_BTCM>;
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memory-region = <&rproc_0_fw_image>;
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};
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r5f@1 {
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compatible = "xlnx,zynqmp-r5f";
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reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>;
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reg-names = "atcm0", "btcm0";
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power-domains = <&zynqmp_firmware PD_RPU_1>,
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<&zynqmp_firmware PD_R5_1_ATCM>,
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<&zynqmp_firmware PD_R5_1_BTCM>;
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memory-region = <&rproc_1_fw_image>;
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};
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};
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amba: axi {
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compatible = "simple-bus";
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bootph-all;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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can0: can@ff060000 {
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compatible = "xlnx,zynq-can-1.0";
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status = "disabled";
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clock-names = "can_clk", "pclk";
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reg = <0x0 0xff060000 0x0 0x1000>;
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interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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tx-fifo-depth = <0x40>;
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rx-fifo-depth = <0x40>;
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resets = <&zynqmp_reset ZYNQMP_RESET_CAN0>;
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power-domains = <&zynqmp_firmware PD_CAN_0>;
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};
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can1: can@ff070000 {
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compatible = "xlnx,zynq-can-1.0";
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status = "disabled";
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clock-names = "can_clk", "pclk";
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reg = <0x0 0xff070000 0x0 0x1000>;
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interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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tx-fifo-depth = <0x40>;
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rx-fifo-depth = <0x40>;
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resets = <&zynqmp_reset ZYNQMP_RESET_CAN1>;
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power-domains = <&zynqmp_firmware PD_CAN_1>;
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};
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cci: cci@fd6e0000 {
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compatible = "arm,cci-400";
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status = "disabled";
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reg = <0x0 0xfd6e0000 0x0 0x9000>;
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ranges = <0x0 0x0 0xfd6e0000 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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pmu@9000 {
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compatible = "arm,cci-400-pmu,r1";
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reg = <0x9000 0x5000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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cpu0_debug: debug@fec10000 {
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compatible = "arm,coresight-cpu-debug", "arm,primecell";
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reg = <0x0 0xfec10000 0x0 0x1000>;
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clock-names = "apb_pclk";
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cpu = <&cpu0>;
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};
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cpu1_debug: debug@fed10000 {
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compatible = "arm,coresight-cpu-debug", "arm,primecell";
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reg = <0x0 0xfed10000 0x0 0x1000>;
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clock-names = "apb_pclk";
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cpu = <&cpu1>;
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};
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cpu2_debug: debug@fee10000 {
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compatible = "arm,coresight-cpu-debug", "arm,primecell";
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reg = <0x0 0xfee10000 0x0 0x1000>;
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clock-names = "apb_pclk";
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cpu = <&cpu2>;
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};
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cpu3_debug: debug@fef10000 {
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compatible = "arm,coresight-cpu-debug", "arm,primecell";
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reg = <0x0 0xfef10000 0x0 0x1000>;
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clock-names = "apb_pclk";
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cpu = <&cpu3>;
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};
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/* GDMA */
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fpd_dma_chan1: dma-controller@fd500000 {
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status = "disabled";
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compatible = "xlnx,zynqmp-dma-1.0";
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reg = <0x0 0xfd500000 0x0 0x1000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "clk_main", "clk_apb";
|
|
#dma-cells = <1>;
|
|
xlnx,bus-width = <128>;
|
|
/* iommus = <&smmu 0x14e8>; */
|
|
power-domains = <&zynqmp_firmware PD_GDMA>;
|
|
};
|
|
|
|
fpd_dma_chan2: dma-controller@fd510000 {
|
|
status = "disabled";
|
|
compatible = "xlnx,zynqmp-dma-1.0";
|
|
reg = <0x0 0xfd510000 0x0 0x1000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "clk_main", "clk_apb";
|
|
#dma-cells = <1>;
|
|
xlnx,bus-width = <128>;
|
|
/* iommus = <&smmu 0x14e9>; */
|
|
power-domains = <&zynqmp_firmware PD_GDMA>;
|
|
};
|
|
|
|
fpd_dma_chan3: dma-controller@fd520000 {
|
|
status = "disabled";
|
|
compatible = "xlnx,zynqmp-dma-1.0";
|
|
reg = <0x0 0xfd520000 0x0 0x1000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "clk_main", "clk_apb";
|
|
#dma-cells = <1>;
|
|
xlnx,bus-width = <128>;
|
|
/* iommus = <&smmu 0x14ea>; */
|
|
power-domains = <&zynqmp_firmware PD_GDMA>;
|
|
};
|
|
|
|
fpd_dma_chan4: dma-controller@fd530000 {
|
|
status = "disabled";
|
|
compatible = "xlnx,zynqmp-dma-1.0";
|
|
reg = <0x0 0xfd530000 0x0 0x1000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "clk_main", "clk_apb";
|
|
#dma-cells = <1>;
|
|
xlnx,bus-width = <128>;
|
|
/* iommus = <&smmu 0x14eb>; */
|
|
power-domains = <&zynqmp_firmware PD_GDMA>;
|
|
};
|
|
|
|
fpd_dma_chan5: dma-controller@fd540000 {
|
|
status = "disabled";
|
|
compatible = "xlnx,zynqmp-dma-1.0";
|
|
reg = <0x0 0xfd540000 0x0 0x1000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "clk_main", "clk_apb";
|
|
#dma-cells = <1>;
|
|
xlnx,bus-width = <128>;
|
|
/* iommus = <&smmu 0x14ec>; */
|
|
power-domains = <&zynqmp_firmware PD_GDMA>;
|
|
};
|
|
|
|
fpd_dma_chan6: dma-controller@fd550000 {
|
|
status = "disabled";
|
|
compatible = "xlnx,zynqmp-dma-1.0";
|
|
reg = <0x0 0xfd550000 0x0 0x1000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "clk_main", "clk_apb";
|
|
#dma-cells = <1>;
|
|
xlnx,bus-width = <128>;
|
|
/* iommus = <&smmu 0x14ed>; */
|
|
power-domains = <&zynqmp_firmware PD_GDMA>;
|
|
};
|
|
|
|
fpd_dma_chan7: dma-controller@fd560000 {
|
|
status = "disabled";
|
|
compatible = "xlnx,zynqmp-dma-1.0";
|
|
reg = <0x0 0xfd560000 0x0 0x1000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "clk_main", "clk_apb";
|
|
#dma-cells = <1>;
|
|
xlnx,bus-width = <128>;
|
|
/* iommus = <&smmu 0x14ee>; */
|
|
power-domains = <&zynqmp_firmware PD_GDMA>;
|
|
};
|
|
|
|
fpd_dma_chan8: dma-controller@fd570000 {
|
|
status = "disabled";
|
|
compatible = "xlnx,zynqmp-dma-1.0";
|
|
reg = <0x0 0xfd570000 0x0 0x1000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "clk_main", "clk_apb";
|
|
#dma-cells = <1>;
|
|
xlnx,bus-width = <128>;
|
|
/* iommus = <&smmu 0x14ef>; */
|
|
power-domains = <&zynqmp_firmware PD_GDMA>;
|
|
};
|
|
|
|
gic: interrupt-controller@f9010000 {
|
|
compatible = "arm,gic-400";
|
|
#interrupt-cells = <3>;
|
|
reg = <0x0 0xf9010000 0x0 0x10000>,
|
|
<0x0 0xf9020000 0x0 0x20000>,
|
|
<0x0 0xf9040000 0x0 0x20000>,
|
|
<0x0 0xf9060000 0x0 0x20000>;
|
|
interrupt-controller;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
};
|
|
|
|
gpu: gpu@fd4b0000 {
|
|
status = "disabled";
|
|
compatible = "xlnx,zynqmp-mali", "arm,mali-400";
|
|
reg = <0x0 0xfd4b0000 0x0 0x10000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1";
|
|
clock-names = "bus", "core";
|
|
power-domains = <&zynqmp_firmware PD_GPU>;
|
|
};
|
|
|
|
/* LPDDMA default allows only secured access. inorder to enable
|
|
* These dma channels, Users should ensure that these dma
|
|
* Channels are allowed for non secure access.
|
|
*/
|
|
lpd_dma_chan1: dma-controller@ffa80000 {
|
|
status = "disabled";
|
|
compatible = "xlnx,zynqmp-dma-1.0";
|
|
reg = <0x0 0xffa80000 0x0 0x1000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "clk_main", "clk_apb";
|
|
#dma-cells = <1>;
|
|
xlnx,bus-width = <64>;
|
|
/* iommus = <&smmu 0x868>; */
|
|
power-domains = <&zynqmp_firmware PD_ADMA>;
|
|
};
|
|
|
|
lpd_dma_chan2: dma-controller@ffa90000 {
|
|
status = "disabled";
|
|
compatible = "xlnx,zynqmp-dma-1.0";
|
|
reg = <0x0 0xffa90000 0x0 0x1000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "clk_main", "clk_apb";
|
|
#dma-cells = <1>;
|
|
xlnx,bus-width = <64>;
|
|
/* iommus = <&smmu 0x869>; */
|
|
power-domains = <&zynqmp_firmware PD_ADMA>;
|
|
};
|
|
|
|
lpd_dma_chan3: dma-controller@ffaa0000 {
|
|
status = "disabled";
|
|
compatible = "xlnx,zynqmp-dma-1.0";
|
|
reg = <0x0 0xffaa0000 0x0 0x1000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "clk_main", "clk_apb";
|
|
#dma-cells = <1>;
|
|
xlnx,bus-width = <64>;
|
|
/* iommus = <&smmu 0x86a>; */
|
|
power-domains = <&zynqmp_firmware PD_ADMA>;
|
|
};
|
|
|
|
lpd_dma_chan4: dma-controller@ffab0000 {
|
|
status = "disabled";
|
|
compatible = "xlnx,zynqmp-dma-1.0";
|
|
reg = <0x0 0xffab0000 0x0 0x1000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "clk_main", "clk_apb";
|
|
#dma-cells = <1>;
|
|
xlnx,bus-width = <64>;
|
|
/* iommus = <&smmu 0x86b>; */
|
|
power-domains = <&zynqmp_firmware PD_ADMA>;
|
|
};
|
|
|
|
lpd_dma_chan5: dma-controller@ffac0000 {
|
|
status = "disabled";
|
|
compatible = "xlnx,zynqmp-dma-1.0";
|
|
reg = <0x0 0xffac0000 0x0 0x1000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "clk_main", "clk_apb";
|
|
#dma-cells = <1>;
|
|
xlnx,bus-width = <64>;
|
|
/* iommus = <&smmu 0x86c>; */
|
|
power-domains = <&zynqmp_firmware PD_ADMA>;
|
|
};
|
|
|
|
lpd_dma_chan6: dma-controller@ffad0000 {
|
|
status = "disabled";
|
|
compatible = "xlnx,zynqmp-dma-1.0";
|
|
reg = <0x0 0xffad0000 0x0 0x1000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "clk_main", "clk_apb";
|
|
#dma-cells = <1>;
|
|
xlnx,bus-width = <64>;
|
|
/* iommus = <&smmu 0x86d>; */
|
|
power-domains = <&zynqmp_firmware PD_ADMA>;
|
|
};
|
|
|
|
lpd_dma_chan7: dma-controller@ffae0000 {
|
|
status = "disabled";
|
|
compatible = "xlnx,zynqmp-dma-1.0";
|
|
reg = <0x0 0xffae0000 0x0 0x1000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "clk_main", "clk_apb";
|
|
#dma-cells = <1>;
|
|
xlnx,bus-width = <64>;
|
|
/* iommus = <&smmu 0x86e>; */
|
|
power-domains = <&zynqmp_firmware PD_ADMA>;
|
|
};
|
|
|
|
lpd_dma_chan8: dma-controller@ffaf0000 {
|
|
status = "disabled";
|
|
compatible = "xlnx,zynqmp-dma-1.0";
|
|
reg = <0x0 0xffaf0000 0x0 0x1000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "clk_main", "clk_apb";
|
|
#dma-cells = <1>;
|
|
xlnx,bus-width = <64>;
|
|
/* iommus = <&smmu 0x86f>; */
|
|
power-domains = <&zynqmp_firmware PD_ADMA>;
|
|
};
|
|
|
|
mc: memory-controller@fd070000 {
|
|
compatible = "xlnx,zynqmp-ddrc-2.40a";
|
|
reg = <0x0 0xfd070000 0x0 0x30000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
nand0: nand-controller@ff100000 {
|
|
compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10";
|
|
status = "disabled";
|
|
reg = <0x0 0xff100000 0x0 0x1000>;
|
|
clock-names = "controller", "bus";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
/* iommus = <&smmu 0x872>; */
|
|
power-domains = <&zynqmp_firmware PD_NAND>;
|
|
};
|
|
|
|
gem0: ethernet@ff0b0000 {
|
|
compatible = "xlnx,zynqmp-gem", "cdns,gem";
|
|
status = "disabled";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0 0xff0b0000 0x0 0x1000>;
|
|
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
|
|
/* iommus = <&smmu 0x874>; */
|
|
power-domains = <&zynqmp_firmware PD_ETH_0>;
|
|
resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>;
|
|
reset-names = "gem0_rst";
|
|
};
|
|
|
|
gem1: ethernet@ff0c0000 {
|
|
compatible = "xlnx,zynqmp-gem", "cdns,gem";
|
|
status = "disabled";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0 0xff0c0000 0x0 0x1000>;
|
|
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
|
|
/* iommus = <&smmu 0x875>; */
|
|
power-domains = <&zynqmp_firmware PD_ETH_1>;
|
|
resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;
|
|
reset-names = "gem1_rst";
|
|
};
|
|
|
|
gem2: ethernet@ff0d0000 {
|
|
compatible = "xlnx,zynqmp-gem", "cdns,gem";
|
|
status = "disabled";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0 0xff0d0000 0x0 0x1000>;
|
|
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
|
|
/* iommus = <&smmu 0x876>; */
|
|
power-domains = <&zynqmp_firmware PD_ETH_2>;
|
|
resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>;
|
|
reset-names = "gem2_rst";
|
|
};
|
|
|
|
gem3: ethernet@ff0e0000 {
|
|
compatible = "xlnx,zynqmp-gem", "cdns,gem";
|
|
status = "disabled";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0 0xff0e0000 0x0 0x1000>;
|
|
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
|
|
/* iommus = <&smmu 0x877>; */
|
|
power-domains = <&zynqmp_firmware PD_ETH_3>;
|
|
resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>;
|
|
reset-names = "gem3_rst";
|
|
};
|
|
|
|
gpio: gpio@ff0a0000 {
|
|
compatible = "xlnx,zynqmp-gpio-1.0";
|
|
status = "disabled";
|
|
#gpio-cells = <0x2>;
|
|
gpio-controller;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x0 0xff0a0000 0x0 0x1000>;
|
|
power-domains = <&zynqmp_firmware PD_GPIO>;
|
|
};
|
|
|
|
i2c0: i2c@ff020000 {
|
|
compatible = "cdns,i2c-r1p14";
|
|
status = "disabled";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-frequency = <400000>;
|
|
reg = <0x0 0xff020000 0x0 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
power-domains = <&zynqmp_firmware PD_I2C_0>;
|
|
};
|
|
|
|
i2c1: i2c@ff030000 {
|
|
compatible = "cdns,i2c-r1p14";
|
|
status = "disabled";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-frequency = <400000>;
|
|
reg = <0x0 0xff030000 0x0 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
power-domains = <&zynqmp_firmware PD_I2C_1>;
|
|
};
|
|
|
|
ocm: memory-controller@ff960000 {
|
|
compatible = "xlnx,zynqmp-ocmc-1.0";
|
|
reg = <0x0 0xff960000 0x0 0x1000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
pcie: pcie@fd0e0000 {
|
|
compatible = "xlnx,nwl-pcie-2.11";
|
|
status = "disabled";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
msi-controller;
|
|
device_type = "pci";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, /* MSI_1 [63...32] */
|
|
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; /* MSI_0 [31...0] */
|
|
interrupt-names = "misc", "dummy", "intx",
|
|
"msi1", "msi0";
|
|
msi-parent = <&pcie>;
|
|
reg = <0x0 0xfd0e0000 0x0 0x1000>,
|
|
<0x0 0xfd480000 0x0 0x1000>,
|
|
<0x80 0x00000000 0x0 0x10000000>;
|
|
reg-names = "breg", "pcireg", "cfg";
|
|
ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */
|
|
<0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
|
|
bus-range = <0x00 0xff>;
|
|
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
|
interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
|
|
<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
|
|
<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
|
|
<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
|
|
/* iommus = <&smmu 0x4d0>; */
|
|
power-domains = <&zynqmp_firmware PD_PCIE>;
|
|
pcie_intc: legacy-interrupt-controller {
|
|
interrupt-controller;
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
};
|
|
};
|
|
|
|
qspi: spi@ff0f0000 {
|
|
bootph-all;
|
|
compatible = "xlnx,zynqmp-qspi-1.0";
|
|
status = "disabled";
|
|
clock-names = "ref_clk", "pclk";
|
|
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-parent = <&gic>;
|
|
num-cs = <1>;
|
|
reg = <0x0 0xff0f0000 0x0 0x1000>,
|
|
<0x0 0xc0000000 0x0 0x8000000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
/* iommus = <&smmu 0x873>; */
|
|
power-domains = <&zynqmp_firmware PD_QSPI>;
|
|
};
|
|
|
|
psgtr: phy@fd400000 {
|
|
compatible = "xlnx,zynqmp-psgtr-v1.1";
|
|
status = "disabled";
|
|
reg = <0x0 0xfd400000 0x0 0x40000>,
|
|
<0x0 0xfd3d0000 0x0 0x1000>;
|
|
reg-names = "serdes", "siou";
|
|
#phy-cells = <4>;
|
|
};
|
|
|
|
rtc: rtc@ffa60000 {
|
|
compatible = "xlnx,zynqmp-rtc";
|
|
status = "disabled";
|
|
reg = <0x0 0xffa60000 0x0 0x100>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "alarm", "sec";
|
|
calibration = <0x7FFF>;
|
|
};
|
|
|
|
sata: ahci@fd0c0000 {
|
|
compatible = "ceva,ahci-1v84";
|
|
status = "disabled";
|
|
reg = <0x0 0xfd0c0000 0x0 0x2000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&zynqmp_firmware PD_SATA>;
|
|
resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
|
|
/* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; */
|
|
};
|
|
|
|
sdhci0: mmc@ff160000 {
|
|
bootph-all;
|
|
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
|
|
status = "disabled";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0 0xff160000 0x0 0x1000>;
|
|
clock-names = "clk_xin", "clk_ahb";
|
|
/* iommus = <&smmu 0x870>; */
|
|
#clock-cells = <1>;
|
|
clock-output-names = "clk_out_sd0", "clk_in_sd0";
|
|
power-domains = <&zynqmp_firmware PD_SD_0>;
|
|
resets = <&zynqmp_reset ZYNQMP_RESET_SDIO0>;
|
|
};
|
|
|
|
sdhci1: mmc@ff170000 {
|
|
bootph-all;
|
|
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
|
|
status = "disabled";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0 0xff170000 0x0 0x1000>;
|
|
clock-names = "clk_xin", "clk_ahb";
|
|
/* iommus = <&smmu 0x871>; */
|
|
#clock-cells = <1>;
|
|
clock-output-names = "clk_out_sd1", "clk_in_sd1";
|
|
power-domains = <&zynqmp_firmware PD_SD_1>;
|
|
resets = <&zynqmp_reset ZYNQMP_RESET_SDIO1>;
|
|
};
|
|
|
|
smmu: iommu@fd800000 {
|
|
compatible = "arm,mmu-500";
|
|
reg = <0x0 0xfd800000 0x0 0x20000>;
|
|
#iommu-cells = <1>;
|
|
status = "disabled";
|
|
#global-interrupts = <1>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
spi0: spi@ff040000 {
|
|
compatible = "cdns,spi-r1p6";
|
|
status = "disabled";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0 0xff040000 0x0 0x1000>;
|
|
clock-names = "ref_clk", "pclk";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
power-domains = <&zynqmp_firmware PD_SPI_0>;
|
|
};
|
|
|
|
spi1: spi@ff050000 {
|
|
compatible = "cdns,spi-r1p6";
|
|
status = "disabled";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0 0xff050000 0x0 0x1000>;
|
|
clock-names = "ref_clk", "pclk";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
power-domains = <&zynqmp_firmware PD_SPI_1>;
|
|
};
|
|
|
|
ttc0: timer@ff110000 {
|
|
compatible = "cdns,ttc";
|
|
status = "disabled";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0 0xff110000 0x0 0x1000>;
|
|
timer-width = <32>;
|
|
power-domains = <&zynqmp_firmware PD_TTC_0>;
|
|
};
|
|
|
|
ttc1: timer@ff120000 {
|
|
compatible = "cdns,ttc";
|
|
status = "disabled";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0 0xff120000 0x0 0x1000>;
|
|
timer-width = <32>;
|
|
power-domains = <&zynqmp_firmware PD_TTC_1>;
|
|
};
|
|
|
|
ttc2: timer@ff130000 {
|
|
compatible = "cdns,ttc";
|
|
status = "disabled";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0 0xff130000 0x0 0x1000>;
|
|
timer-width = <32>;
|
|
power-domains = <&zynqmp_firmware PD_TTC_2>;
|
|
};
|
|
|
|
ttc3: timer@ff140000 {
|
|
compatible = "cdns,ttc";
|
|
status = "disabled";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0 0xff140000 0x0 0x1000>;
|
|
timer-width = <32>;
|
|
power-domains = <&zynqmp_firmware PD_TTC_3>;
|
|
};
|
|
|
|
uart0: serial@ff000000 {
|
|
bootph-all;
|
|
compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
|
|
status = "disabled";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0 0xff000000 0x0 0x1000>;
|
|
clock-names = "uart_clk", "pclk";
|
|
power-domains = <&zynqmp_firmware PD_UART_0>;
|
|
resets = <&zynqmp_reset ZYNQMP_RESET_UART0>;
|
|
};
|
|
|
|
uart1: serial@ff010000 {
|
|
bootph-all;
|
|
compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
|
|
status = "disabled";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0 0xff010000 0x0 0x1000>;
|
|
clock-names = "uart_clk", "pclk";
|
|
power-domains = <&zynqmp_firmware PD_UART_1>;
|
|
resets = <&zynqmp_reset ZYNQMP_RESET_UART1>;
|
|
};
|
|
|
|
usb0: usb@ff9d0000 {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
status = "disabled";
|
|
compatible = "xlnx,zynqmp-dwc3";
|
|
reg = <0x0 0xff9d0000 0x0 0x100>;
|
|
clock-names = "bus_clk", "ref_clk";
|
|
power-domains = <&zynqmp_firmware PD_USB_0>;
|
|
resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,
|
|
<&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,
|
|
<&zynqmp_reset ZYNQMP_RESET_USB0_APB>;
|
|
reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
|
|
reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>;
|
|
ranges;
|
|
|
|
dwc3_0: usb@fe200000 {
|
|
compatible = "snps,dwc3";
|
|
status = "disabled";
|
|
reg = <0x0 0xfe200000 0x0 0x40000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupt-names = "host", "peripheral", "otg", "wakeup";
|
|
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "ref";
|
|
/* iommus = <&smmu 0x860>; */
|
|
snps,quirk-frame-length-adjustment = <0x20>;
|
|
snps,resume-hs-terminations;
|
|
/* dma-coherent; */
|
|
};
|
|
};
|
|
|
|
usb1: usb@ff9e0000 {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
status = "disabled";
|
|
compatible = "xlnx,zynqmp-dwc3";
|
|
reg = <0x0 0xff9e0000 0x0 0x100>;
|
|
clock-names = "bus_clk", "ref_clk";
|
|
power-domains = <&zynqmp_firmware PD_USB_1>;
|
|
resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
|
|
<&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
|
|
<&zynqmp_reset ZYNQMP_RESET_USB1_APB>;
|
|
reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
|
|
ranges;
|
|
|
|
dwc3_1: usb@fe300000 {
|
|
compatible = "snps,dwc3";
|
|
status = "disabled";
|
|
reg = <0x0 0xfe300000 0x0 0x40000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupt-names = "host", "peripheral", "otg", "wakeup";
|
|
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "ref";
|
|
/* iommus = <&smmu 0x861>; */
|
|
snps,quirk-frame-length-adjustment = <0x20>;
|
|
snps,resume-hs-terminations;
|
|
/* dma-coherent; */
|
|
};
|
|
};
|
|
|
|
watchdog0: watchdog@fd4d0000 {
|
|
compatible = "cdns,wdt-r1p2";
|
|
status = "disabled";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>;
|
|
reg = <0x0 0xfd4d0000 0x0 0x1000>;
|
|
timeout-sec = <60>;
|
|
reset-on-timeout;
|
|
};
|
|
|
|
lpd_watchdog: watchdog@ff150000 {
|
|
compatible = "cdns,wdt-r1p2";
|
|
status = "disabled";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>;
|
|
reg = <0x0 0xff150000 0x0 0x1000>;
|
|
timeout-sec = <10>;
|
|
};
|
|
|
|
xilinx_ams: ams@ffa50000 {
|
|
compatible = "xlnx,zynqmp-ams";
|
|
status = "disabled";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0 0xffa50000 0x0 0x800>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
#io-channel-cells = <1>;
|
|
ranges = <0 0 0xffa50800 0x800>;
|
|
|
|
ams_ps: ams-ps@0 {
|
|
compatible = "xlnx,zynqmp-ams-ps";
|
|
status = "disabled";
|
|
reg = <0x0 0x400>;
|
|
};
|
|
|
|
ams_pl: ams-pl@400 {
|
|
compatible = "xlnx,zynqmp-ams-pl";
|
|
status = "disabled";
|
|
reg = <0x400 0x400>;
|
|
};
|
|
};
|
|
|
|
zynqmp_dpdma: dma-controller@fd4c0000 {
|
|
compatible = "xlnx,zynqmp-dpdma";
|
|
status = "disabled";
|
|
reg = <0x0 0xfd4c0000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-parent = <&gic>;
|
|
clock-names = "axi_clk";
|
|
power-domains = <&zynqmp_firmware PD_DP>;
|
|
/* iommus = <&smmu 0xce4>; */
|
|
#dma-cells = <1>;
|
|
};
|
|
|
|
zynqmp_dpsub: display@fd4a0000 {
|
|
bootph-all;
|
|
compatible = "xlnx,zynqmp-dpsub-1.7";
|
|
status = "disabled";
|
|
reg = <0x0 0xfd4a0000 0x0 0x1000>,
|
|
<0x0 0xfd4aa000 0x0 0x1000>,
|
|
<0x0 0xfd4ab000 0x0 0x1000>,
|
|
<0x0 0xfd4ac000 0x0 0x1000>;
|
|
reg-names = "dp", "blend", "av_buf", "aud";
|
|
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-parent = <&gic>;
|
|
/* iommus = <&smmu 0xce3>; */
|
|
clock-names = "dp_apb_clk", "dp_aud_clk",
|
|
"dp_vtc_pixel_clk_in";
|
|
power-domains = <&zynqmp_firmware PD_DP>;
|
|
resets = <&zynqmp_reset ZYNQMP_RESET_DP>;
|
|
dma-names = "vid0", "vid1", "vid2", "gfx0";
|
|
dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>,
|
|
<&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>,
|
|
<&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>,
|
|
<&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>;
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
};
|
|
port@1 {
|
|
reg = <1>;
|
|
};
|
|
port@2 {
|
|
reg = <2>;
|
|
};
|
|
port@3 {
|
|
reg = <3>;
|
|
};
|
|
port@4 {
|
|
reg = <4>;
|
|
};
|
|
port@5 {
|
|
reg = <5>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|