378 lines
6.8 KiB
Plaintext
378 lines
6.8 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* sc7280 CRD 3+ board device tree source
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*
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* Copyright 2022 Google LLC.
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*/
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/dts-v1/;
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#include "sc7280-herobrine.dtsi"
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#include "sc7280-herobrine-audio-wcd9385.dtsi"
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#include "sc7280-herobrine-lte-sku.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev5+)";
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compatible = "google,zoglin", "google,hoglin", "qcom,sc7280";
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/* FIXED REGULATORS */
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/*
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* On most herobrine boards PPVAR_SYS directly provides VREG_EDP_BL.
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* However, on CRD there's an extra regulator in the way. Since this
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* is expected to be uncommon, we'll leave the "vreg_edp_bl" label
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* in the baseboard herobrine.dtsi point at "ppvar_sys" and then
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* make a "_crd" specific version here.
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*/
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vreg_edp_bl_crd: vreg-edp-bl-crd-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vreg_edp_bl_crd";
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gpio = <&pm8350c_gpios 6 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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pinctrl-names = "default";
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pinctrl-0 = <&edp_bl_reg_en>;
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vin-supply = <&ppvar_sys>;
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};
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};
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/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */
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&apps_rsc {
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regulators-2 {
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compatible = "qcom,pmg1110-rpmh-regulators";
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qcom,pmic-id = "k";
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vreg_s1k_1p0: smps1 {
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regulator-min-microvolt = <1010000>;
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regulator-max-microvolt = <1170000>;
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};
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};
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};
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ap_tp_i2c: &i2c0 {
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status = "okay";
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clock-frequency = <400000>;
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trackpad: trackpad@15 {
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compatible = "hid-over-i2c";
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reg = <0x15>;
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pinctrl-names = "default";
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pinctrl-0 = <&tp_int_odl>;
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interrupt-parent = <&tlmm>;
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interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
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post-power-on-delay-ms = <20>;
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hid-descr-addr = <0x0001>;
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vdd-supply = <&pp3300_z1>;
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wakeup-source;
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};
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};
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&ap_sar_sensor_i2c {
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status = "okay";
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};
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&ap_sar_sensor0 {
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status = "okay";
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};
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&ap_sar_sensor1 {
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status = "okay";
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};
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ap_ts_pen_1v8: &i2c13 {
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status = "okay";
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clock-frequency = <400000>;
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ap_ts: touchscreen@5c {
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compatible = "hid-over-i2c";
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reg = <0x5c>;
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pinctrl-names = "default";
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pinctrl-0 = <&ts_int_conn>, <&ts_rst_conn>;
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interrupt-parent = <&tlmm>;
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interrupts = <55 IRQ_TYPE_LEVEL_LOW>;
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post-power-on-delay-ms = <500>;
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hid-descr-addr = <0x0000>;
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vdd-supply = <&pp3300_left_in_mlb>;
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};
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};
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&mdss_edp {
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status = "okay";
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};
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&mdss_edp_phy {
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status = "okay";
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};
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/* For nvme */
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&pcie1 {
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status = "okay";
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};
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/* For nvme */
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&pcie1_phy {
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status = "okay";
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};
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&pm8350c_pwm_backlight {
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power-supply = <&vreg_edp_bl_crd>;
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};
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/* For eMMC */
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&sdhc_1 {
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status = "okay";
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};
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/* For SD Card */
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&sdhc_2 {
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status = "okay";
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};
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/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */
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/*
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* This pin goes to the display panel but then doesn't actually do anything
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* on the panel itself (it doesn't connect to the touchscreen controller).
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* We'll set a pullup here just to park the line.
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*/
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&ts_rst_conn {
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bias-pull-up;
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};
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/* PINCTRL - BOARD-SPECIFIC */
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/*
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* Methodology for gpio-line-names:
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* - If a pin goes to CRD board and is named it gets that name.
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* - If a pin goes to CRD board and is not named, it gets no name.
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* - If a pin is totally internal to Qcard then it gets Qcard name.
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* - If a pin is not hooked up on Qcard, it gets no name.
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*/
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&pm8350c_gpios {
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gpio-line-names = "FLASH_STROBE_1", /* 1 */
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"AP_SUSPEND",
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"PM8008_1_RST_N",
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"",
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"",
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"EDP_BL_REG_EN",
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"PMIC_EDP_BL_EN",
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"PMIC_EDP_BL_PWM",
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"";
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edp_bl_reg_en: edp-bl-reg-en-state {
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pins = "gpio6";
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function = "normal";
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bias-disable;
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qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
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};
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};
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&tlmm {
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gpio-line-names = "AP_TP_I2C_SDA", /* 0 */
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"AP_TP_I2C_SCL",
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"PCIE1_RESET_N",
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"PCIE1_WAKE_N",
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"APPS_I2C_SDA",
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"APPS_I2C_SCL",
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"",
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"TPAD_INT_N",
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"",
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"",
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"GNSS_L1_EN", /* 10 */
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"GNSS_L5_EN",
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"QSPI_DATA_0",
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"QSPI_DATA_1",
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"QSPI_CLK",
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"QSPI_CS_N_1",
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/*
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* AP_FLASH_WP is crossystem ABI. Schematics call it
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* BIOS_FLASH_WP_L (the '_L' suffix is misleading, the
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* signal is active high).
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*/
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"AP_FLASH_WP",
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"",
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"AP_EC_INT_N",
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"",
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"CAM0_RST_N", /* 20 */
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"CAM1_RST_N",
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"SM_DBG_UART_TX",
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"SM_DBG_UART_RX",
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"",
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"PM8008_IRQ_1",
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"HOST2WLAN_SOL",
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"WLAN2HOST_SOL",
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"MOS_BT_UART_CTS",
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"MOS_BT_UART_RFR",
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"MOS_BT_UART_TX", /* 30 */
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"MOS_BT_UART_RX",
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"",
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"HUB_RST",
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"",
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"",
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"",
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"",
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"",
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"",
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"EC_SPI_MISO_GPIO40", /* 40 */
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"EC_SPI_MOSI_GPIO41",
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"EC_SPI_CLK_GPIO42",
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"EC_SPI_CS_GPIO43",
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"",
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"EARLY_EUD_EN",
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"",
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"DP_HOT_PLUG_DETECT",
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"AP_BRD_ID_0",
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"AP_BRD_ID_1",
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"AP_BRD_ID_2", /* 50 */
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"NVME_PWR_REG_EN",
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"TS_I2C_SDA_CONN",
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"TS_I2C_CLK_CONN",
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"TS_RST_CONN",
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"TS_INT_CONN",
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"AP_I2C_TPM_SDA",
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"AP_I2C_TPM_SCL",
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"",
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"",
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"EDP_HOT_PLUG_DET_N", /* 60 */
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"",
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"",
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"AMP_EN",
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"CAM0_MCLK_GPIO_64",
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"CAM1_MCLK_GPIO_65",
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"",
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"",
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"",
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"CCI_I2C_SDA0",
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"CCI_I2C_SCL0", /* 70 */
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"PCIE1_CLK_REQ_N",
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"EN_PP3300_DX_EDP", /* 80 */
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"US_EURO_HS_SEL",
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"FORCED_USB_BOOT",
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"WCD_RESET_N",
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"MOS_WLAN_EN",
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"MOS_BT_EN",
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"MOS_SW_CTRL",
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"MOS_PCIE0_RST",
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"MOS_PCIE0_CLKREQ_N",
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"MOS_PCIE0_WAKE_N",
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"MOS_LAA_AS_EN", /* 90 */
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"SD_CARD_DET_CONN",
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"",
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"",
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"MOS_BT_WLAN_SLIMBUS_CLK",
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"MOS_BT_WLAN_SLIMBUS_DAT0",
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"",
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"",
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"",
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"",
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"", /* 100 */
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"",
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"",
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"",
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"H1_AP_INT_N",
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"",
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"AMP_BCLK",
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"AMP_DIN",
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"AMP_LRCLK",
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"UIM1_DATA_GPIO_109",
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"UIM1_CLK_GPIO_110", /* 110 */
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"UIM1_RESET_GPIO_111",
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"",
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"UIM1_DATA",
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"UIM1_CLK",
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"UIM1_RESET",
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"UIM1_PRESENT",
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"SDM_RFFE0_CLK",
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"SDM_RFFE0_DATA",
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"",
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"SDM_RFFE1_DATA", /* 120 */
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"SC_GPIO_121",
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"FASTBOOT_SEL_1",
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"SC_GPIO_123",
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"FASTBOOT_SEL_2",
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"SM_RFFE4_CLK_GRFC_8",
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"SM_RFFE4_DATA_GRFC_9",
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"WLAN_COEX_UART1_RX",
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"WLAN_COEX_UART1_TX",
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"",
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"", /* 130 */
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"",
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"",
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"SDR_QLINK_REQ",
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"SDR_QLINK_EN",
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"QLINK0_WMSS_RESET_N",
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"SMR526_QLINK1_REQ",
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"SMR526_QLINK1_EN",
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"SMR526_QLINK1_WMSS_RESET_N",
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"",
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"SAR1_INT_N", /* 140 */
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"SAR0_INT_N",
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"",
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"",
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"WCD_SWR_TX_CLK",
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"WCD_SWR_TX_DATA0",
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"WCD_SWR_TX_DATA1",
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"WCD_SWR_RX_CLK",
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"WCD_SWR_RX_DATA0",
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"WCD_SWR_RX_DATA1",
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"DMIC01_CLK", /* 150 */
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"DMIC01_DATA",
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"DMIC23_CLK",
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"DMIC23_DATA",
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"",
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"",
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"EC_IN_RW_N",
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"EN_PP3300_HUB",
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"WCD_SWR_TX_DATA2",
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"",
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"", /* 160 */
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"", /* 170 */
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"MOS_BLE_UART_TX",
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"MOS_BLE_UART_RX",
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"",
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"";
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};
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