124 lines
2.6 KiB
Plaintext
124 lines
2.6 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
|
|
/*
|
|
* Copyright (C) 2020, Intel Corporation.
|
|
*
|
|
* Device tree describing Keem Bay SoC.
|
|
*/
|
|
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
|
|
/ {
|
|
interrupt-parent = <&gic>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu@0 {
|
|
compatible = "arm,cortex-a53";
|
|
device_type = "cpu";
|
|
reg = <0x0>;
|
|
enable-method = "psci";
|
|
};
|
|
|
|
cpu@1 {
|
|
compatible = "arm,cortex-a53";
|
|
device_type = "cpu";
|
|
reg = <0x1>;
|
|
enable-method = "psci";
|
|
};
|
|
|
|
cpu@2 {
|
|
compatible = "arm,cortex-a53";
|
|
device_type = "cpu";
|
|
reg = <0x2>;
|
|
enable-method = "psci";
|
|
};
|
|
|
|
cpu@3 {
|
|
compatible = "arm,cortex-a53";
|
|
device_type = "cpu";
|
|
reg = <0x3>;
|
|
enable-method = "psci";
|
|
};
|
|
};
|
|
|
|
psci {
|
|
compatible = "arm,psci-0.2";
|
|
method = "smc";
|
|
};
|
|
|
|
gic: interrupt-controller@20500000 {
|
|
compatible = "arm,gic-v3";
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
reg = <0x0 0x20500000 0x0 0x20000>, /* GICD */
|
|
<0x0 0x20580000 0x0 0x80000>; /* GICR */
|
|
/* VGIC maintenance interrupt */
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
/* Secure, non-secure, virtual, and hypervisor */
|
|
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
pmu {
|
|
compatible = "arm,cortex-a53-pmu";
|
|
interrupts = <GIC_PPI 0x7 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
soc {
|
|
compatible = "simple-bus";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
uart0: serial@20150000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x0 0x20150000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-frequency = <24000000>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@20160000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x0 0x20160000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-frequency = <24000000>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@20170000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x0 0x20170000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-frequency = <24000000>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@20180000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x0 0x20180000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-frequency = <24000000>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|