48 lines
1.1 KiB
C
48 lines
1.1 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
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/*
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* Copyright 2024 NXP
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*/
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#ifndef __IMX95_POWER_H__
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#define __IMX95_POWER_H__
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#define IMX95_PD_ANA 0
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#define IMX95_PD_AON 1
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#define IMX95_PD_BBSM 2
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#define IMX95_PD_CAMERA 3
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#define IMX95_PD_CCMSRCGPC 4
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#define IMX95_PD_A55C0 5
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#define IMX95_PD_A55C1 6
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#define IMX95_PD_A55C2 7
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#define IMX95_PD_A55C3 8
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#define IMX95_PD_A55C4 9
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#define IMX95_PD_A55C5 10
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#define IMX95_PD_A55P 11
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#define IMX95_PD_DDR 12
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#define IMX95_PD_DISPLAY 13
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#define IMX95_PD_GPU 14
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#define IMX95_PD_HSIO_TOP 15
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#define IMX95_PD_HSIO_WAON 16
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#define IMX95_PD_M7 17
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#define IMX95_PD_NETC 18
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#define IMX95_PD_NOC 19
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#define IMX95_PD_NPU 20
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#define IMX95_PD_VPU 21
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#define IMX95_PD_WAKEUP 22
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#define IMX95_PERF_ELE 0
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#define IMX95_PERF_M33 1
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#define IMX95_PERF_WAKEUP 2
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#define IMX95_PERF_M7 3
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#define IMX95_PERF_DRAM 4
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#define IMX95_PERF_HSIO 5
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#define IMX95_PERF_NPU 6
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#define IMX95_PERF_NOC 7
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#define IMX95_PERF_A55 8
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#define IMX95_PERF_GPU 9
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#define IMX95_PERF_VPU 10
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#define IMX95_PERF_CAM 11
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#define IMX95_PERF_DISP 12
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#endif
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