529 lines
12 KiB
Plaintext
529 lines
12 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 PHYTEC Messtechnik GmbH
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* Author: Teresa Remmet <t.remmet@phytec.de>
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*/
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/dts-v1/;
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#include <dt-bindings/phy/phy-imx8-pcie.h>
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#include <dt-bindings/leds/leds-pca9532.h>
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#include <dt-bindings/pwm/pwm.h>
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#include "imx8mp-phycore-som.dtsi"
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/ {
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model = "PHYTEC phyBOARD-Pollux i.MX8MP";
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compatible = "phytec,imx8mp-phyboard-pollux-rdk",
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"phytec,imx8mp-phycore-som", "fsl,imx8mp";
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chosen {
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stdout-path = &uart1;
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};
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backlight_lvds: backlight {
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compatible = "pwm-backlight";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lvds1>;
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brightness-levels = <0 4 8 16 32 64 128 255>;
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default-brightness-level = <11>;
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enable-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
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num-interpolated-steps = <2>;
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power-supply = <®_lvds1_reg_en>;
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pwms = <&pwm3 0 50000 0>;
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};
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panel1_lvds: panel-lvds {
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compatible = "edt,etml1010g3dra";
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backlight = <&backlight_lvds>;
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power-supply = <®_vcc_3v3_sw>;
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port {
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panel1_in: endpoint {
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remote-endpoint = <&ldb_lvds_ch1>;
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};
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};
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};
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reg_vcc_5v_sw: regulator-vcc-5v-sw {
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compatible = "regulator-fixed";
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <5000000>;
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regulator-min-microvolt = <5000000>;
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regulator-name = "VCC_5V_SW";
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};
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reg_can1_stby: regulator-can1-stby {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1_reg>;
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gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <3300000>;
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regulator-name = "can1-stby";
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};
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reg_can2_stby: regulator-can2-stby {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan2_reg>;
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gpio = <&gpio3 21 GPIO_ACTIVE_LOW>;
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <3300000>;
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regulator-name = "can2-stby";
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};
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reg_lvds1_reg_en: regulator-lvds1 {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
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regulator-max-microvolt = <1200000>;
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regulator-min-microvolt = <1200000>;
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regulator-name = "lvds1_reg_en";
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};
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reg_usb1_vbus: regulator-usb1-vbus {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb1_vbus>;
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gpio = <&gpio1 12 GPIO_ACTIVE_LOW>;
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regulator-max-microvolt = <5000000>;
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regulator-min-microvolt = <5000000>;
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regulator-name = "usb1_host_vbus";
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};
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reg_usdhc2_vmmc: regulator-usdhc2 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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startup-delay-us = <100>;
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off-on-delay-us = <12000>;
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};
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reg_vcc_3v3_sw: regulator-vcc-3v3-sw {
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compatible = "regulator-fixed";
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regulator-name = "VCC_3V3_SW";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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/* TPM */
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&ecspi1 {
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#address-cells = <1>;
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#size-cells = <0>;
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cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi1>;
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status = "okay";
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tpm: tpm@0 {
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compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
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reg = <0>;
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spi-max-frequency = <38000000>;
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};
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};
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&eqos {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_eqos>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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status = "okay";
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mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0x1>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
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enet-phy-lane-no-swap;
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};
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};
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};
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/* CAN FD */
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&flexcan1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1>;
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xceiver-supply = <®_can1_stby>;
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status = "okay";
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};
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&flexcan2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan2>;
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xceiver-supply = <®_can2_stby>;
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status = "okay";
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};
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&i2c2 {
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clock-frequency = <400000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c2>;
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pinctrl-1 = <&pinctrl_i2c2_gpio>;
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sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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status = "okay";
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eeprom@51 {
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compatible = "atmel,24c02";
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reg = <0x51>;
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pagesize = <16>;
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vcc-supply = <®_vcc_3v3_sw>;
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};
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leds@62 {
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compatible = "nxp,pca9533";
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reg = <0x62>;
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led-1 {
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type = <PCA9532_TYPE_LED>;
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};
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led-2 {
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type = <PCA9532_TYPE_LED>;
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};
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led-3 {
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type = <PCA9532_TYPE_LED>;
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};
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};
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};
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&lcdif2 {
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status = "okay";
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};
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&lvds_bridge {
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status = "okay";
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ports {
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port@2 {
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ldb_lvds_ch1: endpoint {
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remote-endpoint = <&panel1_in>;
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};
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};
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};
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};
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&media_blk_ctrl {
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/*
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* The LVDS panel on this device uses 72.4 MHz pixel clock,
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* set IMX8MP_VIDEO_PLL1 to 72.4 * 7 = 506.8 MHz so the LDB
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* serializer and LCDIFv3 scanout engine can reach accurate
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* pixel clock of exactly 72.4 MHz.
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*/
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assigned-clock-rates = <500000000>, <200000000>,
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<0>, <0>, <500000000>,
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<506800000>;
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};
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&snvs_pwrkey {
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status = "okay";
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};
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&pcie_phy {
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clocks = <&hsio_blk_ctrl>;
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clock-names = "ref";
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fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
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fsl,clkreq-unsupported;
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status = "okay";
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};
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/* Mini PCIe */
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&pcie {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pcie0>;
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reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
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vpcie-supply = <®_vcc_3v3_sw>;
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status = "okay";
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};
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&pwm3 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm3>;
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};
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&rv3028 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_rtc>;
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interrupt-parent = <&gpio4>;
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interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
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aux-voltage-chargeable = <1>;
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wakeup-source;
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trickle-resistor-ohms = <3000>;
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};
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/* debug console */
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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/* USB1 Host mode Type-A */
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&usb3_phy0 {
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vbus-supply = <®_usb1_vbus>;
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status = "okay";
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};
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&usb3_0 {
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status = "okay";
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};
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&usb_dwc3_0 {
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dr_mode = "host";
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status = "okay";
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};
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/* USB2 4-port USB3.0 HUB */
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&usb3_phy1 {
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vbus-supply = <®_vcc_5v_sw>;
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status = "okay";
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};
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&usb3_1 {
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fsl,permanently-attached;
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fsl,disable-port-power-control;
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status = "okay";
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};
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&usb_dwc3_1 {
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dr_mode = "host";
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status = "okay";
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};
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/* RS232/RS485 */
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&uart2 {
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assigned-clocks = <&clk IMX8MP_CLK_UART2>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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uart-has-rtscts;
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status = "okay";
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};
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/* SD-Card */
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&usdhc2 {
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assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
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assigned-clock-rates = <200000000>;
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_pins>;
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cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
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disable-wp;
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vmmc-supply = <®_usdhc2_vmmc>;
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vqmmc-supply = <&ldo5>;
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bus-width = <4>;
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status = "okay";
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};
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&gpio1 {
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gpio-line-names = "", "", "X_PMIC_WDOG_B", "",
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"PMIC_SD_VSEL", "", "", "", "", "",
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"", "", "USB1_OTG_PWR", "", "", "X_nETHPHY_INT";
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};
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&gpio2 {
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gpio-line-names = "", "", "", "",
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"", "", "", "", "", "",
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"", "", "X_SD2_CD_B", "", "", "",
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"", "", "", "SD2_RESET_B";
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};
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&gpio3 {
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gpio-line-names = "", "", "", "",
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"", "", "", "", "", "",
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"", "", "", "", "", "",
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"", "", "", "", "nCAN1_EN", "nCAN2_EN";
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};
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&gpio4 {
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gpio-line-names = "", "", "", "",
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"", "", "", "", "", "",
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"", "", "", "", "", "",
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"", "", "X_PMIC_IRQ_B", "", "nENET0_INT_PWDN";
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};
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&iomuxc {
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pinctrl_ecspi1: ecspi1grp {
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fsl,pins = <
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MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x80
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MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x80
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MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x80
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MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x00
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>;
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};
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pinctrl_eqos: eqosgrp {
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fsl,pins = <
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MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
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MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
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MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
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MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
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MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
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MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
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MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
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MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
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MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12
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MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12
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MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12
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MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12
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MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12
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MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x12
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MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10
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>;
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};
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pinctrl_flexcan1: flexcan1grp {
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fsl,pins = <
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MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154
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MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154
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>;
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};
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pinctrl_flexcan2: flexcan2grp {
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fsl,pins = <
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MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
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MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
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>;
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};
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pinctrl_flexcan1_reg: flexcan1reggrp {
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fsl,pins = <
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MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x154
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>;
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};
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pinctrl_flexcan2_reg: flexcan2reggrp {
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fsl,pins = <
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MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x154
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
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MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
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>;
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};
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pinctrl_i2c2_gpio: i2c2gpiogrp {
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fsl,pins = <
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MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e2
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MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e2
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>;
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};
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pinctrl_lvds1: lvds1grp {
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fsl,pins = <
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MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x12
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>;
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};
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pinctrl_pcie0: pcie0grp {
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fsl,pins = <
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MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x40
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MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x60
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MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x60 /* open drain, pull up */
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MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x40
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>;
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};
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pinctrl_pwm3: pwm3grp {
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fsl,pins = <
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MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x12
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>;
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};
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pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
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fsl,pins = <
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MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
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>;
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};
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pinctrl_rtc: rtcgrp {
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fsl,pins = <
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MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1C0
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
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MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
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>;
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};
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pinctrl_usb1_vbus: usb1vbusgrp {
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fsl,pins = <
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MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x10
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
|
|
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
|
|
MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x140
|
|
MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x140
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_pins: usdhc2-gpiogrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x40
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2: usdhc2grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
|
|
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
|
|
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
|
|
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
|
|
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
|
|
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
|
|
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
|
|
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
|
|
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
|
|
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
|
|
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
|
|
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
|
|
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
|
|
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
|
|
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
|
|
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
|
|
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
|
|
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
|
|
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
|
|
>;
|
|
};
|
|
};
|