378 lines
6.0 KiB
Plaintext
378 lines
6.0 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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//
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// Device Tree file for LX2162A Clearfog
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//
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// Copyright 2023 Josua Mayer <josua@solid-run.com>
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/dts-v1/;
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#include "fsl-lx2160a.dtsi"
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#include "fsl-lx2162a-sr-som.dtsi"
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/ {
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model = "SolidRun LX2162A Clearfog";
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compatible = "solidrun,lx2162a-clearfog", "solidrun,lx2162a-som", "fsl,lx2160a";
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aliases {
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crypto = &crypto;
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i2c0 = &i2c0;
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i2c1 = &i2c2;
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i2c2 = &i2c4;
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i2c3 = &sfp_i2c0;
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i2c4 = &sfp_i2c1;
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i2c5 = &sfp_i2c2;
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i2c6 = &sfp_i2c3;
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i2c7 = &mpcie1_i2c;
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i2c8 = &mpcie0_i2c;
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i2c9 = &pcieclk_i2c;
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i2c10 = &i2c5;
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mmc0 = &esdhc0;
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mmc1 = &esdhc1;
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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leds {
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compatible = "gpio-leds";
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led_sfp_at: led-sfp-at {
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gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* PROC_IRQ5 */
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default-state = "off";
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};
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led_sfp_ab: led-sfp-ab {
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gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; /* PROC_IRQ11 */
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default-state = "off";
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};
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led_sfp_bt: led-sfp-bt {
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gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; /* EVT1_B */
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default-state = "off";
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};
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led_sfp_bb: led-sfp-bb {
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gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; /* EVT2_B */
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default-state = "off";
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};
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};
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sfp_at: sfp-at {
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compatible = "sff,sfp";
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i2c-bus = <&sfp_i2c0>;
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mod-def0-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>; /* EVT4_B */
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maximum-power-milliwatt = <2000>;
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};
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sfp_ab: sfp-ab {
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compatible = "sff,sfp";
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i2c-bus = <&sfp_i2c1>;
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mod-def0-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; /* PROC_IRQ1 */
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maximum-power-milliwatt = <2000>;
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};
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sfp_bt: sfp-bt {
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compatible = "sff,sfp";
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i2c-bus = <&sfp_i2c2>;
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mod-def0-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; /* PROC_IRQ10 */
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maximum-power-milliwatt = <2000>;
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};
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sfp_bb: sfp-bb {
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compatible = "sff,sfp";
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i2c-bus = <&sfp_i2c3>;
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mod-def0-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; /* EVT3_B */
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maximum-power-milliwatt = <2000>;
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};
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};
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&dpmac3 {
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sfp = <&sfp_at>;
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managed = "in-band-status";
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phys = <&serdes_1 7>;
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};
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&dpmac4 {
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sfp = <&sfp_ab>;
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managed = "in-band-status";
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phys = <&serdes_1 6>;
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};
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&dpmac5 {
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sfp = <&sfp_bt>;
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managed = "in-band-status";
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phys = <&serdes_1 5>;
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};
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&dpmac6 {
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sfp = <&sfp_bb>;
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managed = "in-band-status";
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phys = <&serdes_1 4>;
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};
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&dpmac11 {
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phys = <&serdes_2 0>;
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phy-handle = <ðernet_phy3>;
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phy-connection-type = "sgmii";
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status = "okay";
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};
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&dpmac12 {
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phys = <&serdes_2 1>;
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phy-handle = <ðernet_phy1>;
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phy-connection-type = "sgmii";
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status = "okay";
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};
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&dpmac13 {
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phys = <&serdes_2 6>;
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phy-handle = <ðernet_phy6>;
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phy-connection-type = "sgmii";
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status = "okay";
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};
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&dpmac14 {
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phys = <&serdes_2 7>;
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phy-handle = <ðernet_phy8>;
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phy-connection-type = "sgmii";
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status = "okay";
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};
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&dpmac15 {
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phys = <&serdes_2 4>;
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phy-handle = <ðernet_phy4>;
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phy-connection-type = "sgmii";
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status = "okay";
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};
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&dpmac16 {
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phys = <&serdes_2 5>;
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phy-handle = <ðernet_phy2>;
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phy-connection-type = "sgmii";
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status = "okay";
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};
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&dpmac17 {
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/* override connection to on-SoM phy */
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/delete-property/ phy-handle;
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/delete-property/ phy-connection-type;
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phys = <&serdes_2 2>;
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phy-handle = <ðernet_phy5>;
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phy-connection-type = "sgmii";
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status = "okay";
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};
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&dpmac18 {
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phys = <&serdes_2 3>;
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phy-handle = <ðernet_phy7>;
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phy-connection-type = "sgmii";
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status = "okay";
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};
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&emdio1 {
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ethernet_phy1: ethernet-phy@8 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <8>;
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max-speed = <1000>;
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};
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ethernet_phy2: ethernet-phy@9 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <9>;
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max-speed = <1000>;
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};
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ethernet_phy3: ethernet-phy@10 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <10>;
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max-speed = <1000>;
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};
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ethernet_phy4: ethernet-phy@11 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <11>;
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max-speed = <1000>;
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};
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ethernet_phy5: ethernet-phy@12 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <12>;
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max-speed = <1000>;
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};
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ethernet_phy6: ethernet-phy@13 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <13>;
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max-speed = <1000>;
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};
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ethernet_phy7: ethernet-phy@14 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <14>;
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max-speed = <1000>;
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};
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ethernet_phy8: ethernet-phy@15 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <15>;
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max-speed = <1000>;
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};
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};
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&esdhc0 {
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sd-uhs-sdr104;
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sd-uhs-sdr50;
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sd-uhs-sdr25;
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sd-uhs-sdr12;
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status = "okay";
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};
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ðernet_phy0 {
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/*
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* SoM has a phy at address 1 connected to SoC Ethernet Controller 1.
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* It competes for WRIOP MAC17, and no connector has been wired.
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*/
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status = "disabled";
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};
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&i2c2 {
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status = "okay";
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/* retimer@18 */
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i2c-mux@70 {
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compatible = "nxp,pca9546";
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reg = <0x70>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c-mux-idle-disconnect;
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sfp_i2c0: i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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};
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sfp_i2c1: i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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};
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sfp_i2c2: i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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};
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sfp_i2c3: i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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};
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};
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i2c-mux@71 {
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compatible = "nxp,pca9546";
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reg = <0x71>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c-mux-idle-disconnect;
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mpcie1_i2c: i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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};
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mpcie0_i2c: i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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};
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pcieclk_i2c: i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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/* clock-controller@6b */
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};
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};
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};
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&pcie3 {
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status = "disabled";
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};
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&pcie4 {
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status = "disabled";
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};
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&pcs_mdio3 {
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status = "okay";
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};
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&pcs_mdio4 {
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status = "okay";
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};
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&pcs_mdio5 {
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status = "okay";
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};
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&pcs_mdio6 {
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status = "okay";
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};
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&pcs_mdio11 {
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status = "okay";
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};
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&pcs_mdio12 {
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status = "okay";
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};
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&pcs_mdio13 {
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status = "okay";
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};
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&pcs_mdio14 {
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status = "okay";
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};
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&pcs_mdio15 {
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status = "okay";
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};
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&pcs_mdio16 {
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status = "okay";
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};
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&pcs_mdio17 {
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status = "okay";
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};
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&pcs_mdio18 {
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status = "okay";
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};
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&serdes_1 {
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status = "okay";
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};
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&serdes_2 {
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status = "okay";
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};
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&uart0 {
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status = "okay";
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};
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&usb0 {
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status = "okay";
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};
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