122 lines
3.2 KiB
Plaintext
122 lines
3.2 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2023 BayLibre, SAS.
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* Author: Jerome Brunet <jbrunet@baylibre.com>
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*/
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/dts-v1/;
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#include <dt-bindings/clock/g12a-clkc.h>
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#include "meson-g12b-a311d.dtsi"
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#include "meson-libretech-cottonwood.dtsi"
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/ {
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compatible = "libretech,aml-a311d-cc", "amlogic,a311d", "amlogic,g12b";
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model = "Libre Computer AML-A311D-CC Alta";
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vddcpu_a: regulator-vddcpu-a {
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compatible = "pwm-regulator";
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regulator-name = "VDDCPU_A";
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regulator-min-microvolt = <730000>;
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regulator-max-microvolt = <1011000>;
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regulator-boot-on;
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regulator-always-on;
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pwm-supply = <&dc_in>;
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pwms = <&pwm_ab 0 1250 0>;
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pwm-dutycycle-range = <100 0>;
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};
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sound {
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model = "LC-ALTA";
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audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
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"TDMOUT_A IN 1", "FRDDR_B OUT 0",
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"TDMOUT_A IN 2", "FRDDR_C OUT 0",
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"TDM_A Playback", "TDMOUT_A OUT",
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"TDMOUT_B IN 0", "FRDDR_A OUT 1",
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"TDMOUT_B IN 1", "FRDDR_B OUT 1",
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"TDMOUT_B IN 2", "FRDDR_C OUT 1",
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"TDM_B Playback", "TDMOUT_B OUT",
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"TDMOUT_C IN 0", "FRDDR_A OUT 2",
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"TDMOUT_C IN 1", "FRDDR_B OUT 2",
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"TDMOUT_C IN 2", "FRDDR_C OUT 2",
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"TDM_C Playback", "TDMOUT_C OUT",
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"TDMIN_A IN 0", "TDM_A Capture",
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"TDMIN_B IN 0", "TDM_A Capture",
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"TDMIN_C IN 0", "TDM_A Capture",
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"TDMIN_A IN 3", "TDM_A Loopback",
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"TDMIN_B IN 3", "TDM_A Loopback",
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"TDMIN_C IN 3", "TDM_A Loopback",
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"TDMIN_A IN 1", "TDM_B Capture",
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"TDMIN_B IN 1", "TDM_B Capture",
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"TDMIN_C IN 1", "TDM_B Capture",
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"TDMIN_A IN 4", "TDM_B Loopback",
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"TDMIN_B IN 4", "TDM_B Loopback",
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"TDMIN_C IN 4", "TDM_B Loopback",
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"TDMIN_A IN 2", "TDM_C Capture",
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"TDMIN_B IN 2", "TDM_C Capture",
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"TDMIN_C IN 2", "TDM_C Capture",
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"TDMIN_A IN 5", "TDM_C Loopback",
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"TDMIN_B IN 5", "TDM_C Loopback",
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"TDMIN_C IN 5", "TDM_C Loopback",
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"TODDR_A IN 0", "TDMIN_A OUT",
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"TODDR_B IN 0", "TDMIN_A OUT",
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"TODDR_C IN 0", "TDMIN_A OUT",
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"TODDR_A IN 1", "TDMIN_B OUT",
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"TODDR_B IN 1", "TDMIN_B OUT",
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"TODDR_C IN 1", "TDMIN_B OUT",
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"TODDR_A IN 2", "TDMIN_C OUT",
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"TODDR_B IN 2", "TDMIN_C OUT",
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"TODDR_C IN 2", "TDMIN_C OUT",
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"Lineout", "ACODEC LOLP",
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"Lineout", "ACODEC LORP";
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};
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};
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&cpu0 {
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cpu-supply = <&vddcpu_b>;
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operating-points-v2 = <&cpu_opp_table_0>;
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clocks = <&clkc CLKID_CPU_CLK>;
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clock-latency = <50000>;
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};
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&cpu1 {
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cpu-supply = <&vddcpu_b>;
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operating-points-v2 = <&cpu_opp_table_0>;
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clocks = <&clkc CLKID_CPU_CLK>;
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clock-latency = <50000>;
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};
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&cpu100 {
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cpu-supply = <&vddcpu_a>;
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operating-points-v2 = <&cpub_opp_table_1>;
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clocks = <&clkc CLKID_CPUB_CLK>;
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clock-latency = <50000>;
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};
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&cpu101 {
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cpu-supply = <&vddcpu_a>;
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operating-points-v2 = <&cpub_opp_table_1>;
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clocks = <&clkc CLKID_CPUB_CLK>;
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clock-latency = <50000>;
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};
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&cpu102 {
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cpu-supply = <&vddcpu_a>;
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operating-points-v2 = <&cpub_opp_table_1>;
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clocks = <&clkc CLKID_CPUB_CLK>;
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clock-latency = <50000>;
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};
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&cpu103 {
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cpu-supply = <&vddcpu_a>;
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operating-points-v2 = <&cpub_opp_table_1>;
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clocks = <&clkc CLKID_CPUB_CLK>;
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clock-latency = <50000>;
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};
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&pwm_ab {
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pinctrl-0 = <&pwm_a_e_pins>, <&pwm_b_x7_pins>;
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clocks = <&xtal>, <&xtal>;
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clock-names = "clkin0", "clkin1";
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};
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