628 lines
15 KiB
Plaintext
628 lines
15 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2021 Amlogic, Inc. All rights reserved.
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/reset/amlogic,c3-reset.h>
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#include <dt-bindings/clock/amlogic,c3-pll-clkc.h>
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#include <dt-bindings/clock/amlogic,c3-scmi-clkc.h>
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#include <dt-bindings/clock/amlogic,c3-peripherals-clkc.h>
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#include <dt-bindings/power/amlogic,c3-pwrc.h>
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#include <dt-bindings/gpio/amlogic-c3-gpio.h>
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/ {
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x0 0x0>;
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enable-method = "psci";
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x0 0x1>;
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enable-method = "psci";
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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xtal: xtal-clk {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "xtal";
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#clock-cells = <0>;
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};
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sm: secure-monitor {
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compatible = "amlogic,meson-gxbb-sm";
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pwrc: power-controller {
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compatible = "amlogic,c3-pwrc";
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#power-domain-cells = <1>;
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};
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};
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sram@7f50e00 {
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compatible = "mmio-sram";
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reg = <0x0 0x07f50e00 0x0 0x100>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x0 0x07f50e00 0x100>;
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scmi_shmem: sram@0 {
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compatible = "arm,scmi-shmem";
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reg = <0x0 0x100>;
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};
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};
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firmware {
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scmi: scmi {
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compatible = "arm,scmi-smc";
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arm,smc-id = <0x820000C1>;
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shmem = <&scmi_shmem>;
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#address-cells = <1>;
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#size-cells = <0>;
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scmi_clk: protocol@14 {
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reg = <0x14>;
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#clock-cells = <1>;
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};
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gic: interrupt-controller@fff01000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x0 0xfff01000 0 0x1000>,
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<0x0 0xfff02000 0 0x2000>,
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<0x0 0xfff04000 0 0x2000>,
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<0x0 0xfff06000 0 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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apb4: bus@fe000000 {
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compatible = "simple-bus";
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reg = <0x0 0xfe000000 0x0 0x480000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
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clkc_periphs: clock-controller@0 {
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compatible = "amlogic,c3-peripherals-clkc";
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reg = <0x0 0x0 0x0 0x49c>;
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#clock-cells = <1>;
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clocks = <&xtal>,
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<&scmi_clk CLKID_OSC>,
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<&scmi_clk CLKID_FIXED_PLL_OSC>,
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<&clkc_pll CLKID_FCLK_DIV2>,
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<&clkc_pll CLKID_FCLK_DIV2P5>,
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<&clkc_pll CLKID_FCLK_DIV3>,
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<&clkc_pll CLKID_FCLK_DIV4>,
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<&clkc_pll CLKID_FCLK_DIV5>,
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<&clkc_pll CLKID_FCLK_DIV7>,
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<&clkc_pll CLKID_GP0_PLL>,
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<&scmi_clk CLKID_GP1_PLL_OSC>,
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<&clkc_pll CLKID_HIFI_PLL>,
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<&scmi_clk CLKID_SYS_CLK>,
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<&scmi_clk CLKID_AXI_CLK>,
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<&scmi_clk CLKID_SYS_PLL_DIV16>,
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<&scmi_clk CLKID_CPU_CLK_DIV16>;
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clock-names = "xtal_24m",
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"oscin",
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"fix",
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"fdiv2",
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"fdiv2p5",
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"fdiv3",
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"fdiv4",
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"fdiv5",
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"fdiv7",
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"gp0",
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"gp1",
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"hifi",
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"sysclk",
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"axiclk",
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"sysplldiv16",
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"cpudiv16";
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};
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reset: reset-controller@2000 {
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compatible = "amlogic,c3-reset";
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reg = <0x0 0x2000 0x0 0x98>;
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#reset-cells = <1>;
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};
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watchdog@2100 {
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compatible = "amlogic,c3-wdt", "amlogic,t7-wdt";
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reg = <0x0 0x2100 0x0 0x10>;
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clocks = <&xtal>;
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};
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periphs_pinctrl: pinctrl@4000 {
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compatible = "amlogic,c3-periphs-pinctrl";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0x4000 0x0 0x02de>;
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gpio: bank@0 {
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reg = <0x0 0x0 0x0 0x004c>,
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<0x0 0x100 0x0 0x01de>;
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reg-names = "mux", "gpio";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&periphs_pinctrl 0 0 55>;
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};
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i2c0_pins1: i2c0-pins1 {
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mux {
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groups = "i2c0_sda_e",
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"i2c0_scl_e";
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function = "i2c0";
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bias-disable;
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drive-strength-microamp = <3000>;
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};
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};
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i2c0_pins2: i2c0-pins2 {
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mux {
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groups = "i2c0_sda_d",
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"i2c0_scl_d";
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function = "i2c0";
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bias-disable;
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drive-strength-microamp = <3000>;
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};
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};
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i2c1_pins1: i2c1-pins1 {
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mux {
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groups = "i2c1_sda_x",
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"i2c1_scl_x";
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function = "i2c1";
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bias-disable;
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drive-strength-microamp = <3000>;
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};
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};
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i2c1_pins2: i2c1-pins2 {
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mux {
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groups = "i2c1_sda_d",
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"i2c1_scl_d";
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function = "i2c1";
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bias-disable;
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drive-strength-microamp = <3000>;
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};
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};
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i2c1_pins3: i2c1-pins3 {
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mux {
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groups = "i2c1_sda_a",
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"i2c1_scl_a";
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function = "i2c1";
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bias-disable;
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drive-strength-microamp = <3000>;
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};
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};
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i2c1_pins4: i2c1-pins4 {
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mux {
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groups = "i2c1_sda_b",
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"i2c1_scl_b";
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function = "i2c1";
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bias-disable;
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drive-strength-microamp = <3000>;
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};
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};
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i2c2_pins1: i2c2-pins1 {
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mux {
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groups = "i2c2_sda",
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"i2c2_scl";
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function = "i2c2";
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bias-disable;
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drive-strength-microamp = <3000>;
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};
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};
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i2c3_pins1: i2c3-pins1 {
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mux {
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groups = "i2c3_sda_c",
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"i2c3_scl_c";
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function = "i2c3";
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bias-disable;
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drive-strength-microamp = <3000>;
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};
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};
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i2c3_pins2: i2c3-pins2 {
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mux {
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groups = "i2c3_sda_x",
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"i2c3_scl_x";
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function = "i2c3";
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bias-disable;
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drive-strength-microamp = <3000>;
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};
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};
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i2c3_pins3: i2c3-pins3 {
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mux {
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groups = "i2c3_sda_d",
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"i2c3_scl_d";
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function = "i2c3";
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bias-disable;
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drive-strength-microamp = <3000>;
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};
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};
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nand_pins: nand-pins {
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mux {
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groups = "emmc_nand_d0",
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"emmc_nand_d1",
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"emmc_nand_d2",
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"emmc_nand_d3",
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"emmc_nand_d4",
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"emmc_nand_d5",
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"emmc_nand_d6",
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"emmc_nand_d7",
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"nand_ce0",
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"nand_ale",
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"nand_cle",
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"nand_wen_clk",
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"nand_ren_wr";
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function = "nand";
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input-enable;
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};
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};
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sdcard_pins: sdcard-pins {
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mux {
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groups = "sdcard_d0",
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"sdcard_d1",
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"sdcard_d2",
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"sdcard_d3",
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"sdcard_clk",
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"sdcard_cmd";
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function = "sdcard";
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bias-pull-up;
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drive-strength-microamp = <4000>;
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};
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};
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sdcard_clk_gate_pins: sdcard-clk-cmd-pins {
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mux {
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groups = "GPIOC_4";
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function = "gpio_periphs";
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bias-pull-down;
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drive-strength-microamp = <4000>;
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};
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};
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sdio_m_clk_gate_pins: sdio-m-clk-cmd-pins {
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mux {
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groups = "sdio_clk";
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function = "sdio";
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bias-pull-down;
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drive-strength-microamp = <4000>;
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};
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};
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sdio_m_pins: sdio-m-all-pins {
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mux {
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groups = "sdio_d0",
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"sdio_d1",
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"sdio_d2",
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"sdio_d3",
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"sdio_clk",
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"sdio_cmd";
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function = "sdio";
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input-enable;
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bias-pull-up;
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drive-strength-microamp = <4000>;
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};
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};
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spicc0_pins1: spicc0-pins1 {
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mux {
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groups = "spi_a_mosi_b",
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"spi_a_miso_b",
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"spi_a_clk_b";
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function = "spi_a";
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drive-strength-microamp = <3000>;
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};
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};
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spicc0_pins2: spicc0-pins2 {
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mux {
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groups = "spi_a_mosi_c",
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"spi_a_miso_c",
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"spi_a_clk_c";
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function = "spi_a";
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drive-strength-microamp = <3000>;
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};
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};
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spicc0_pins3: spicc0-pins3 {
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mux {
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groups = "spi_a_mosi_x",
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"spi_a_miso_x",
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"spi_a_clk_x";
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function = "spi_a";
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drive-strength-microamp = <3000>;
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};
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};
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spicc1_pins1: spicc1-pins1 {
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mux {
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groups = "spi_b_mosi_d",
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"spi_b_miso_d",
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"spi_b_clk_d";
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function = "spi_b";
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drive-strength-microamp = <3000>;
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};
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};
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spicc1_pins2: spicc1-pins2 {
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mux {
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groups = "spi_b_mosi_x",
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"spi_b_miso_x",
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"spi_b_clk_x";
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function = "spi_b";
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drive-strength-microamp = <3000>;
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};
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};
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spifc_pins: spifc-pins {
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mux {
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groups = "spif_mo",
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"spif_mi",
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"spif_clk",
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"spif_cs",
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"spif_hold",
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"spif_wp",
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"spif_clk_loop";
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function = "spif";
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drive-strength-microamp = <4000>;
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};
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};
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};
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gpio_intc: interrupt-controller@4080 {
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compatible = "amlogic,c3-gpio-intc", "amlogic,meson-gpio-intc";
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reg = <0x0 0x4080 0x0 0x0020>;
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interrupt-controller;
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#interrupt-cells = <2>;
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amlogic,channel-interrupts =
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<10 11 12 13 14 15 16 17 18 19 20 21>;
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};
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clkc_pll: clock-controller@8000 {
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compatible = "amlogic,c3-pll-clkc";
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reg = <0x0 0x8000 0x0 0x1a4>;
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#clock-cells = <1>;
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clocks = <&scmi_clk CLKID_TOP_PLL_OSC>,
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<&scmi_clk CLKID_MCLK_PLL_OSC>,
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<&scmi_clk CLKID_FIXED_PLL_OSC>;
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clock-names = "top",
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"mclk",
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"fix";
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};
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eth_phy: mdio-multiplexer@28000 {
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compatible = "amlogic,g12a-mdio-mux";
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reg = <0x0 0x28000 0x0 0xa4>;
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clocks = <&clkc_periphs CLKID_SYS_ETH_PHY>,
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<&xtal>,
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<&clkc_pll CLKID_FCLK_50M>;
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clock-names = "pclk", "clkin0", "clkin1";
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mdio-parent-bus = <&mdio0>;
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#address-cells = <1>;
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#size-cells = <0>;
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ext_mdio: mdio@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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int_mdio: mdio@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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internal_ephy: ethernet_phy@8 {
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compatible = "ethernet-phy-id0180.3301",
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"ethernet-phy-ieee802.3-c22";
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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reg = <8>;
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max-speed = <100>;
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};
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};
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};
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spicc0: spi@50000 {
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compatible = "amlogic,meson-g12a-spicc";
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reg = <0x0 0x50000 0x0 0x44>;
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interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clkc_periphs CLKID_SYS_SPICC_0>,
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<&clkc_periphs CLKID_SPICC_A>;
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clock-names = "core", "pclk";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spicc1: spi@52000 {
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compatible = "amlogic,meson-g12a-spicc";
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reg = <0x0 0x52000 0x0 0x44>;
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interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clkc_periphs CLKID_SYS_SPICC_1>,
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<&clkc_periphs CLKID_SPICC_B>;
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clock-names = "core", "pclk";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spifc: spi@56000 {
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compatible = "amlogic,a1-spifc";
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reg = <0x0 0x56000 0x0 0x290>;
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interrupts = <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>;
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clocks = <&clkc_periphs CLKID_SPIFC>;
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clock-names = "core";
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status = "disabled";
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};
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i2c0: i2c@66000 {
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compatible = "amlogic,meson-axg-i2c";
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reg = <0x0 0x66000 0x0 0x24>;
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interrupts = <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clkc_periphs CLKID_SYS_I2C_M_A>;
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status = "disabled";
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};
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i2c1: i2c@68000 {
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compatible = "amlogic,meson-axg-i2c";
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reg = <0x0 0x68000 0x0 0x24>;
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interrupts = <GIC_SPI 161 IRQ_TYPE_EDGE_RISING>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clkc_periphs CLKID_SYS_I2C_M_B>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@6a000 {
|
|
compatible = "amlogic,meson-axg-i2c";
|
|
reg = <0x0 0x6a000 0x0 0x24>;
|
|
interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clkc_periphs CLKID_SYS_I2C_M_C>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@6c000 {
|
|
compatible = "amlogic,meson-axg-i2c";
|
|
reg = <0x0 0x6c000 0x0 0x24>;
|
|
interrupts = <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clkc_periphs CLKID_SYS_I2C_M_D>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart_b: serial@7a000 {
|
|
compatible = "amlogic,meson-s4-uart",
|
|
"amlogic,meson-ao-uart";
|
|
reg = <0x0 0x7a000 0x0 0x18>;
|
|
interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
|
|
status = "disabled";
|
|
clocks = <&xtal>, <&clkc_periphs CLKID_SYS_UART_B>, <&xtal>;
|
|
clock-names = "xtal", "pclk", "baud";
|
|
};
|
|
|
|
sec_ao: ao-secure@10220 {
|
|
compatible = "amlogic,c3-ao-secure",
|
|
"amlogic,meson-gx-ao-secure",
|
|
"syscon";
|
|
reg = <0x0 0x10220 0x0 0x140>;
|
|
amlogic,has-chip-id;
|
|
};
|
|
|
|
sdio: mmc@88000 {
|
|
compatible = "amlogic,meson-axg-mmc";
|
|
reg = <0x0 0x88000 0x0 0x800>;
|
|
interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>;
|
|
power-domains = <&pwrc PWRC_C3_SDIOA_ID>;
|
|
clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_A>,
|
|
<&clkc_periphs CLKID_SD_EMMC_A>,
|
|
<&clkc_pll CLKID_FCLK_DIV2>;
|
|
clock-names = "core","clkin0", "clkin1";
|
|
no-mmc;
|
|
no-sd;
|
|
resets = <&reset RESET_SD_EMMC_A>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sd: mmc@8a000 {
|
|
compatible = "amlogic,meson-axg-mmc";
|
|
reg = <0x0 0x8a000 0x0 0x800>;
|
|
interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
|
|
power-domains = <&pwrc PWRC_C3_SDCARD_ID>;
|
|
clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_B>,
|
|
<&clkc_periphs CLKID_SD_EMMC_B>,
|
|
<&clkc_pll CLKID_FCLK_DIV2>;
|
|
clock-names = "core", "clkin0", "clkin1";
|
|
no-mmc;
|
|
no-sdio;
|
|
resets = <&reset RESET_SD_EMMC_B>;
|
|
status = "disabled";
|
|
};
|
|
|
|
nand: nand-controller@8d000 {
|
|
compatible = "amlogic,meson-axg-nfc";
|
|
reg = <0x0 0x8d000 0x0 0x200>,
|
|
<0x0 0x8C000 0x0 0x4>;
|
|
reg-names = "nfc", "emmc";
|
|
interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>;
|
|
clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_C>,
|
|
<&clkc_pll CLKID_FCLK_DIV2>;
|
|
clock-names = "core", "device";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
ethmac: ethernet@fdc00000 {
|
|
compatible = "amlogic,meson-g12a-dwmac",
|
|
"snps,dwmac-3.70a",
|
|
"snps,dwmac";
|
|
reg = <0x0 0xfdc00000 0x0 0x10000>,
|
|
<0x0 0xfe024000 0x0 0x8>;
|
|
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq";
|
|
power-domains = <&pwrc PWRC_C3_ETH_ID>;
|
|
clocks = <&clkc_periphs CLKID_SYS_ETH_MAC>,
|
|
<&clkc_pll CLKID_FCLK_DIV2>,
|
|
<&clkc_pll CLKID_FCLK_50M>;
|
|
clock-names = "stmmaceth", "clkin0", "clkin1";
|
|
rx-fifo-depth = <4096>;
|
|
tx-fifo-depth = <2048>;
|
|
status = "disabled";
|
|
|
|
mdio0: mdio {
|
|
compatible = "snps,dwmac-mdio";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
};
|
|
};
|