589 lines
22 KiB
Plaintext
589 lines
22 KiB
Plaintext
What: /sys/bus/cxl/flush
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Date: Januarry, 2022
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KernelVersion: v5.18
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Contact: linux-cxl@vger.kernel.org
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Description:
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(WO) If userspace manually unbinds a port the kernel schedules
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all descendant memdevs for unbind. Writing '1' to this attribute
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flushes that work.
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What: /sys/bus/cxl/devices/memX/firmware_version
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Date: December, 2020
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KernelVersion: v5.12
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) "FW Revision" string as reported by the Identify
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Memory Device Output Payload in the CXL-2.0
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specification.
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What: /sys/bus/cxl/devices/memX/ram/size
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Date: December, 2020
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KernelVersion: v5.12
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) "Volatile Only Capacity" as bytes. Represents the
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identically named field in the Identify Memory Device Output
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Payload in the CXL-2.0 specification.
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What: /sys/bus/cxl/devices/memX/ram/qos_class
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Date: May, 2023
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KernelVersion: v6.8
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) For CXL host platforms that support "QoS Telemmetry"
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this attribute conveys a comma delimited list of platform
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specific cookies that identifies a QoS performance class
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for the volatile partition of the CXL mem device. These
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class-ids can be compared against a similar "qos_class"
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published for a root decoder. While it is not required
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that the endpoints map their local memory-class to a
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matching platform class, mismatches are not recommended
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and there are platform specific performance related
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side-effects that may result. First class-id is displayed.
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What: /sys/bus/cxl/devices/memX/pmem/size
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Date: December, 2020
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KernelVersion: v5.12
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) "Persistent Only Capacity" as bytes. Represents the
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identically named field in the Identify Memory Device Output
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Payload in the CXL-2.0 specification.
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What: /sys/bus/cxl/devices/memX/pmem/qos_class
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Date: May, 2023
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KernelVersion: v6.8
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) For CXL host platforms that support "QoS Telemmetry"
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this attribute conveys a comma delimited list of platform
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specific cookies that identifies a QoS performance class
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for the persistent partition of the CXL mem device. These
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class-ids can be compared against a similar "qos_class"
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published for a root decoder. While it is not required
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that the endpoints map their local memory-class to a
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matching platform class, mismatches are not recommended
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and there are platform specific performance related
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side-effects that may result. First class-id is displayed.
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What: /sys/bus/cxl/devices/memX/serial
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Date: January, 2022
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KernelVersion: v5.18
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) 64-bit serial number per the PCIe Device Serial Number
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capability. Mandatory for CXL devices, see CXL 2.0 8.1.12.2
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Memory Device PCIe Capabilities and Extended Capabilities.
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What: /sys/bus/cxl/devices/memX/numa_node
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Date: January, 2022
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KernelVersion: v5.18
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) If NUMA is enabled and the platform has affinitized the
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host PCI device for this memory device, emit the CPU node
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affinity for this device.
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What: /sys/bus/cxl/devices/memX/security/state
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Date: June, 2023
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KernelVersion: v6.5
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) Reading this file will display the CXL security state for
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that device. Such states can be: 'disabled', 'sanitize', when
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a sanitization is currently underway; or those available only
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for persistent memory: 'locked', 'unlocked' or 'frozen'. This
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sysfs entry is select/poll capable from userspace to notify
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upon completion of a sanitize operation.
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What: /sys/bus/cxl/devices/memX/security/sanitize
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Date: June, 2023
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KernelVersion: v6.5
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Contact: linux-cxl@vger.kernel.org
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Description:
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(WO) Write a boolean 'true' string value to this attribute to
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sanitize the device to securely re-purpose or decommission it.
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This is done by ensuring that all user data and meta-data,
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whether it resides in persistent capacity, volatile capacity,
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or the LSA, is made permanently unavailable by whatever means
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is appropriate for the media type. This functionality requires
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the device to be disabled, that is, not actively decoding any
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HPA ranges. This permits avoiding explicit global CPU cache
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management, relying instead for it to be done when a region
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transitions between software programmed and hardware committed
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states. If this file is not present, then there is no hardware
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support for the operation.
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What /sys/bus/cxl/devices/memX/security/erase
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Date: June, 2023
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KernelVersion: v6.5
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Contact: linux-cxl@vger.kernel.org
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Description:
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(WO) Write a boolean 'true' string value to this attribute to
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secure erase user data by changing the media encryption keys for
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all user data areas of the device. This functionality requires
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the device to be disabled, that is, not actively decoding any
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HPA ranges. This permits avoiding explicit global CPU cache
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management, relying instead for it to be done when a region
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transitions between software programmed and hardware committed
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states. If this file is not present, then there is no hardware
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support for the operation.
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What: /sys/bus/cxl/devices/memX/firmware/
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Date: April, 2023
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KernelVersion: v6.5
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RW) Firmware uploader mechanism. The different files under
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this directory can be used to upload and activate new
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firmware for CXL devices. The interfaces under this are
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documented in sysfs-class-firmware.
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What: /sys/bus/cxl/devices/*/devtype
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Date: June, 2021
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KernelVersion: v5.14
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) CXL device objects export the devtype attribute which
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mirrors the same value communicated in the DEVTYPE environment
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variable for uevents for devices on the "cxl" bus.
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What: /sys/bus/cxl/devices/*/modalias
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Date: December, 2021
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KernelVersion: v5.18
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) CXL device objects export the modalias attribute which
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mirrors the same value communicated in the MODALIAS environment
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variable for uevents for devices on the "cxl" bus.
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What: /sys/bus/cxl/devices/portX/uport
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Date: June, 2021
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KernelVersion: v5.14
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) CXL port objects are enumerated from either a platform
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firmware device (ACPI0017 and ACPI0016) or PCIe switch upstream
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port with CXL component registers. The 'uport' symlink connects
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the CXL portX object to the device that published the CXL port
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capability.
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What: /sys/bus/cxl/devices/{port,endpoint}X/parent_dport
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Date: January, 2023
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KernelVersion: v6.3
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) CXL port objects are instantiated for each upstream port in
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a CXL/PCIe switch, and for each endpoint to map the
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corresponding memory device into the CXL port hierarchy. When a
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descendant CXL port (switch or endpoint) is enumerated it is
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useful to know which 'dport' object in the parent CXL port
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routes to this descendant. The 'parent_dport' symlink points to
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the device representing the downstream port of a CXL switch that
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routes to {port,endpoint}X.
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What: /sys/bus/cxl/devices/portX/dportY
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Date: June, 2021
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KernelVersion: v5.14
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) CXL port objects are enumerated from either a platform
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firmware device (ACPI0017 and ACPI0016) or PCIe switch upstream
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port with CXL component registers. The 'dportY' symlink
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identifies one or more downstream ports that the upstream port
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may target in its decode of CXL memory resources. The 'Y'
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integer reflects the hardware port unique-id used in the
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hardware decoder target list.
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What: /sys/bus/cxl/devices/portX/decoders_committed
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Date: October, 2023
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KernelVersion: v6.7
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) A memory device is considered active when any of its
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decoders are in the "committed" state (See CXL 3.0 8.2.4.19.7
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CXL HDM Decoder n Control Register). Hotplug and destructive
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operations like "sanitize" are blocked while device is actively
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decoding a Host Physical Address range. Note that this number
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may be elevated without any regionX objects active or even
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enumerated, as this may be due to decoders established by
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platform firwmare or a previous kernel (kexec).
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What: /sys/bus/cxl/devices/decoderX.Y
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Date: June, 2021
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KernelVersion: v5.14
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) CXL decoder objects are enumerated from either a platform
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firmware description, or a CXL HDM decoder register set in a
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PCIe device (see CXL 2.0 section 8.2.5.12 CXL HDM Decoder
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Capability Structure). The 'X' in decoderX.Y represents the
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cxl_port container of this decoder, and 'Y' represents the
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instance id of a given decoder resource.
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What: /sys/bus/cxl/devices/decoderX.Y/{start,size}
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Date: June, 2021
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KernelVersion: v5.14
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) The 'start' and 'size' attributes together convey the
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physical address base and number of bytes mapped in the
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decoder's decode window. For decoders of devtype
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"cxl_decoder_root" the address range is fixed. For decoders of
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devtype "cxl_decoder_switch" the address is bounded by the
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decode range of the cxl_port ancestor of the decoder's cxl_port,
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and dynamically updates based on the active memory regions in
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that address space.
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What: /sys/bus/cxl/devices/decoderX.Y/locked
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Date: June, 2021
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KernelVersion: v5.14
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) CXL HDM decoders have the capability to lock the
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configuration until the next device reset. For decoders of
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devtype "cxl_decoder_root" there is no standard facility to
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unlock them. For decoders of devtype "cxl_decoder_switch" a
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secondary bus reset, of the PCIe bridge that provides the bus
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for this decoders uport, unlocks / resets the decoder.
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What: /sys/bus/cxl/devices/decoderX.Y/target_list
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Date: June, 2021
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KernelVersion: v5.14
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) Display a comma separated list of the current decoder
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target configuration. The list is ordered by the current
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configured interleave order of the decoder's dport instances.
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Each entry in the list is a dport id.
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What: /sys/bus/cxl/devices/decoderX.Y/cap_{pmem,ram,type2,type3}
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Date: June, 2021
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KernelVersion: v5.14
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) When a CXL decoder is of devtype "cxl_decoder_root", it
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represents a fixed memory window identified by platform
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firmware. A fixed window may only support a subset of memory
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types. The 'cap_*' attributes indicate whether persistent
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memory, volatile memory, accelerator memory, and / or expander
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memory may be mapped behind this decoder's memory window.
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What: /sys/bus/cxl/devices/decoderX.Y/target_type
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Date: June, 2021
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KernelVersion: v5.14
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) When a CXL decoder is of devtype "cxl_decoder_switch", it
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can optionally decode either accelerator memory (type-2) or
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expander memory (type-3). The 'target_type' attribute indicates
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the current setting which may dynamically change based on what
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memory regions are activated in this decode hierarchy.
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What: /sys/bus/cxl/devices/endpointX/CDAT
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Date: July, 2022
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KernelVersion: v6.0
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) If this sysfs entry is not present no DOE mailbox was
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found to support CDAT data. If it is present and the length of
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the data is 0 reading the CDAT data failed. Otherwise the CDAT
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data is reported.
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What: /sys/bus/cxl/devices/decoderX.Y/mode
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Date: May, 2022
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KernelVersion: v6.0
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it
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translates from a host physical address range, to a device local
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address range. Device-local address ranges are further split
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into a 'ram' (volatile memory) range and 'pmem' (persistent
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memory) range. The 'mode' attribute emits one of 'ram', 'pmem',
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'mixed', or 'none'. The 'mixed' indication is for error cases
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when a decoder straddles the volatile/persistent partition
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boundary, and 'none' indicates the decoder is not actively
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decoding, or no DPA allocation policy has been set.
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'mode' can be written, when the decoder is in the 'disabled'
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state, with either 'ram' or 'pmem' to set the boundaries for the
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next allocation.
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What: /sys/bus/cxl/devices/decoderX.Y/dpa_resource
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Date: May, 2022
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KernelVersion: v6.0
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) When a CXL decoder is of devtype "cxl_decoder_endpoint",
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and its 'dpa_size' attribute is non-zero, this attribute
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indicates the device physical address (DPA) base address of the
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allocation.
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What: /sys/bus/cxl/devices/decoderX.Y/dpa_size
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Date: May, 2022
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KernelVersion: v6.0
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it
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translates from a host physical address range, to a device local
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address range. The range, base address plus length in bytes, of
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DPA allocated to this decoder is conveyed in these 2 attributes.
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Allocations can be mutated as long as the decoder is in the
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disabled state. A write to 'dpa_size' releases the previous DPA
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allocation and then attempts to allocate from the free capacity
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in the device partition referred to by 'decoderX.Y/mode'.
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Allocate and free requests can only be performed on the highest
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instance number disabled decoder with non-zero size. I.e.
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allocations are enforced to occur in increasing 'decoderX.Y/id'
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order and frees are enforced to occur in decreasing
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'decoderX.Y/id' order.
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What: /sys/bus/cxl/devices/decoderX.Y/interleave_ways
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Date: May, 2022
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KernelVersion: v6.0
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) The number of targets across which this decoder's host
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physical address (HPA) memory range is interleaved. The device
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maps every Nth block of HPA (of size ==
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'interleave_granularity') to consecutive DPA addresses. The
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decoder's position in the interleave is determined by the
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device's (endpoint or switch) switch ancestry. For root
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decoders their interleave is specified by platform firmware and
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they only specify a downstream target order for host bridges.
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What: /sys/bus/cxl/devices/decoderX.Y/interleave_granularity
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Date: May, 2022
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KernelVersion: v6.0
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) The number of consecutive bytes of host physical address
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space this decoder claims at address N before the decode rotates
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to the next target in the interleave at address N +
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interleave_granularity (assuming N is aligned to
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interleave_granularity).
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What: /sys/bus/cxl/devices/decoderX.Y/create_{pmem,ram}_region
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Date: May, 2022, January, 2023
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KernelVersion: v6.0 (pmem), v6.3 (ram)
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RW) Write a string in the form 'regionZ' to start the process
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of defining a new persistent, or volatile memory region
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(interleave-set) within the decode range bounded by root decoder
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'decoderX.Y'. The value written must match the current value
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returned from reading this attribute. An atomic compare exchange
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operation is done on write to assign the requested id to a
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region and allocate the region-id for the next creation attempt.
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EBUSY is returned if the region name written does not match the
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current cached value.
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What: /sys/bus/cxl/devices/decoderX.Y/delete_region
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Date: May, 2022
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KernelVersion: v6.0
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Contact: linux-cxl@vger.kernel.org
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Description:
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(WO) Write a string in the form 'regionZ' to delete that region,
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provided it is currently idle / not bound to a driver.
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What: /sys/bus/cxl/devices/decoderX.Y/qos_class
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Date: May, 2023
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KernelVersion: v6.5
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) For CXL host platforms that support "QoS Telemmetry" this
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root-decoder-only attribute conveys a platform specific cookie
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that identifies a QoS performance class for the CXL Window.
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This class-id can be compared against a similar "qos_class"
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published for each memory-type that an endpoint supports. While
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it is not required that endpoints map their local memory-class
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to a matching platform class, mismatches are not recommended and
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there are platform specific side-effects that may result.
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What: /sys/bus/cxl/devices/regionZ/uuid
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Date: May, 2022
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KernelVersion: v6.0
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RW) Write a unique identifier for the region. This field must
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be set for persistent regions and it must not conflict with the
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UUID of another region. For volatile ram regions this
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attribute is a read-only empty string.
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What: /sys/bus/cxl/devices/regionZ/interleave_granularity
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Date: May, 2022
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KernelVersion: v6.0
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RW) Set the number of consecutive bytes each device in the
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interleave set will claim. The possible interleave granularity
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values are determined by the CXL spec and the participating
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devices.
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What: /sys/bus/cxl/devices/regionZ/interleave_ways
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Date: May, 2022
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KernelVersion: v6.0
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RW) Configures the number of devices participating in the
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region is set by writing this value. Each device will provide
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1/interleave_ways of storage for the region.
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What: /sys/bus/cxl/devices/regionZ/size
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Date: May, 2022
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KernelVersion: v6.0
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RW) System physical address space to be consumed by the region.
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When written trigger the driver to allocate space out of the
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|
parent root decoder's address space. When read the size of the
|
|
address space is reported and should match the span of the
|
|
region's resource attribute. Size shall be set after the
|
|
interleave configuration parameters. Once set it cannot be
|
|
changed, only freed by writing 0. The kernel makes no guarantees
|
|
that data is maintained over an address space freeing event, and
|
|
there is no guarantee that a free followed by an allocate
|
|
results in the same address being allocated.
|
|
|
|
|
|
What: /sys/bus/cxl/devices/regionZ/mode
|
|
Date: January, 2023
|
|
KernelVersion: v6.3
|
|
Contact: linux-cxl@vger.kernel.org
|
|
Description:
|
|
(RO) The mode of a region is established at region creation time
|
|
and dictates the mode of the endpoint decoder that comprise the
|
|
region. For more details on the possible modes see
|
|
/sys/bus/cxl/devices/decoderX.Y/mode
|
|
|
|
|
|
What: /sys/bus/cxl/devices/regionZ/resource
|
|
Date: May, 2022
|
|
KernelVersion: v6.0
|
|
Contact: linux-cxl@vger.kernel.org
|
|
Description:
|
|
(RO) A region is a contiguous partition of a CXL root decoder
|
|
address space. Region capacity is allocated by writing to the
|
|
size attribute, the resulting physical address space determined
|
|
by the driver is reflected here. It is therefore not useful to
|
|
read this before writing a value to the size attribute.
|
|
|
|
|
|
What: /sys/bus/cxl/devices/regionZ/target[0..N]
|
|
Date: May, 2022
|
|
KernelVersion: v6.0
|
|
Contact: linux-cxl@vger.kernel.org
|
|
Description:
|
|
(RW) Write an endpoint decoder object name to 'targetX' where X
|
|
is the intended position of the endpoint device in the region
|
|
interleave and N is the 'interleave_ways' setting for the
|
|
region. ENXIO is returned if the write results in an impossible
|
|
to map decode scenario, like the endpoint is unreachable at that
|
|
position relative to the root decoder interleave. EBUSY is
|
|
returned if the position in the region is already occupied, or
|
|
if the region is not in a state to accept interleave
|
|
configuration changes. EINVAL is returned if the object name is
|
|
not an endpoint decoder. Once all positions have been
|
|
successfully written a final validation for decode conflicts is
|
|
performed before activating the region.
|
|
|
|
|
|
What: /sys/bus/cxl/devices/regionZ/commit
|
|
Date: May, 2022
|
|
KernelVersion: v6.0
|
|
Contact: linux-cxl@vger.kernel.org
|
|
Description:
|
|
(RW) Write a boolean 'true' string value to this attribute to
|
|
trigger the region to transition from the software programmed
|
|
state to the actively decoding in hardware state. The commit
|
|
operation in addition to validating that the region is in proper
|
|
configured state, validates that the decoders are being
|
|
committed in spec mandated order (last committed decoder id +
|
|
1), and checks that the hardware accepts the commit request.
|
|
Reading this value indicates whether the region is committed or
|
|
not.
|
|
|
|
|
|
What: /sys/bus/cxl/devices/memX/trigger_poison_list
|
|
Date: April, 2023
|
|
KernelVersion: v6.4
|
|
Contact: linux-cxl@vger.kernel.org
|
|
Description:
|
|
(WO) When a boolean 'true' is written to this attribute the
|
|
memdev driver retrieves the poison list from the device. The
|
|
list consists of addresses that are poisoned, or would result
|
|
in poison if accessed, and the source of the poison. This
|
|
attribute is only visible for devices supporting the
|
|
capability. The retrieved errors are logged as kernel
|
|
events when cxl_poison event tracing is enabled.
|
|
|
|
|
|
What: /sys/bus/cxl/devices/regionZ/accessY/read_bandwidth
|
|
/sys/bus/cxl/devices/regionZ/accessY/write_banwidth
|
|
Date: Jan, 2024
|
|
KernelVersion: v6.9
|
|
Contact: linux-cxl@vger.kernel.org
|
|
Description:
|
|
(RO) The aggregated read or write bandwidth of the region. The
|
|
number is the accumulated read or write bandwidth of all CXL memory
|
|
devices that contributes to the region in MB/s. It is
|
|
identical data that should appear in
|
|
/sys/devices/system/node/nodeX/accessY/initiators/read_bandwidth or
|
|
/sys/devices/system/node/nodeX/accessY/initiators/write_bandwidth.
|
|
See Documentation/ABI/stable/sysfs-devices-node. access0 provides
|
|
the number to the closest initiator and access1 provides the
|
|
number to the closest CPU.
|
|
|
|
|
|
What: /sys/bus/cxl/devices/regionZ/accessY/read_latency
|
|
/sys/bus/cxl/devices/regionZ/accessY/write_latency
|
|
Date: Jan, 2024
|
|
KernelVersion: v6.9
|
|
Contact: linux-cxl@vger.kernel.org
|
|
Description:
|
|
(RO) The read or write latency of the region. The number is
|
|
the worst read or write latency of all CXL memory devices that
|
|
contributes to the region in nanoseconds. It is identical data
|
|
that should appear in
|
|
/sys/devices/system/node/nodeX/accessY/initiators/read_latency or
|
|
/sys/devices/system/node/nodeX/accessY/initiators/write_latency.
|
|
See Documentation/ABI/stable/sysfs-devices-node. access0 provides
|
|
the number to the closest initiator and access1 provides the
|
|
number to the closest CPU.
|