150 lines
5.5 KiB
Plaintext
150 lines
5.5 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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menuconfig CXL_BUS
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tristate "CXL (Compute Express Link) Devices Support"
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depends on PCI
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select FW_LOADER
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select FW_UPLOAD
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select PCI_DOE
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select FIRMWARE_TABLE
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select NUMA_KEEP_MEMINFO if (NUMA && X86)
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help
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CXL is a bus that is electrically compatible with PCI Express, but
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layers three protocols on that signalling (CXL.io, CXL.cache, and
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CXL.mem). The CXL.cache protocol allows devices to hold cachelines
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locally, the CXL.mem protocol allows devices to be fully coherent
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memory targets, the CXL.io protocol is equivalent to PCI Express.
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Say 'y' to enable support for the configuration and management of
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devices supporting these protocols.
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if CXL_BUS
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config CXL_PCI
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tristate "PCI manageability"
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default CXL_BUS
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help
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The CXL specification defines a "CXL memory device" sub-class in the
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PCI "memory controller" base class of devices. Device's identified by
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this class code provide support for volatile and / or persistent
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memory to be mapped into the system address map (Host-managed Device
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Memory (HDM)).
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Say 'y/m' to enable a driver that will attach to CXL memory expander
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devices enumerated by the memory device class code for configuration
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and management primarily via the mailbox interface. See Chapter 2.3
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Type 3 CXL Device in the CXL 2.0 specification for more details.
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If unsure say 'm'.
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config CXL_MEM_RAW_COMMANDS
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bool "RAW Command Interface for Memory Devices"
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depends on CXL_PCI
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help
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Enable CXL RAW command interface.
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The CXL driver ioctl interface may assign a kernel ioctl command
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number for each specification defined opcode. At any given point in
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time the number of opcodes that the specification defines and a device
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may implement may exceed the kernel's set of associated ioctl function
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numbers. The mismatch is either by omission, specification is too new,
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or by design. When prototyping new hardware, or developing / debugging
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the driver it is useful to be able to submit any possible command to
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the hardware, even commands that may crash the kernel due to their
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potential impact to memory currently in use by the kernel.
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If developing CXL hardware or the driver say Y, otherwise say N.
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config CXL_ACPI
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tristate "CXL ACPI: Platform Support"
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depends on ACPI
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depends on ACPI_NUMA
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default CXL_BUS
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select ACPI_TABLE_LIB
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select ACPI_HMAT
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select CXL_PORT
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help
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Enable support for host managed device memory (HDM) resources
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published by a platform's ACPI CXL memory layout description. See
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Chapter 9.14.1 CXL Early Discovery Table (CEDT) in the CXL 2.0
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specification, and CXL Fixed Memory Window Structures (CEDT.CFMWS)
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(https://www.computeexpresslink.org/spec-landing). The CXL core
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consumes these resource to publish the root of a cxl_port decode
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hierarchy to map regions that represent System RAM, or Persistent
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Memory regions to be managed by LIBNVDIMM.
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If unsure say 'm'.
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config CXL_PMEM
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tristate "CXL PMEM: Persistent Memory Support"
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depends on LIBNVDIMM
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default CXL_BUS
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help
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In addition to typical memory resources a platform may also advertise
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support for persistent memory attached via CXL. This support is
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managed via a bridge driver from CXL to the LIBNVDIMM system
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subsystem. Say 'y/m' to enable support for enumerating and
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provisioning the persistent memory capacity of CXL memory expanders.
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If unsure say 'm'.
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config CXL_MEM
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tristate "CXL: Memory Expansion"
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depends on CXL_PCI
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default CXL_BUS
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help
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The CXL.mem protocol allows a device to act as a provider of "System
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RAM" and/or "Persistent Memory" that is fully coherent as if the
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memory were attached to the typical CPU memory controller. This is
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known as HDM "Host-managed Device Memory".
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Say 'y/m' to enable a driver that will attach to CXL.mem devices for
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memory expansion and control of HDM. See Chapter 9.13 in the CXL 2.0
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specification for a detailed description of HDM.
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If unsure say 'm'.
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config CXL_PORT
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default CXL_BUS
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tristate
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config CXL_SUSPEND
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def_bool y
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depends on SUSPEND && CXL_MEM
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config CXL_REGION
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bool "CXL: Region Support"
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default CXL_BUS
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# For MAX_PHYSMEM_BITS
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depends on SPARSEMEM
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select MEMREGION
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select GET_FREE_REGION
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help
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Enable the CXL core to enumerate and provision CXL regions. A CXL
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region is defined by one or more CXL expanders that decode a given
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system-physical address range. For CXL regions established by
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platform-firmware this option enables memory error handling to
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identify the devices participating in a given interleaved memory
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range. Otherwise, platform-firmware managed CXL is enabled by being
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placed in the system address map and does not need a driver.
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If unsure say 'y'
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config CXL_REGION_INVALIDATION_TEST
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bool "CXL: Region Cache Management Bypass (TEST)"
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depends on CXL_REGION
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help
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CXL Region management and security operations potentially invalidate
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the content of CPU caches without notifying those caches to
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invalidate the affected cachelines. The CXL Region driver attempts
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to invalidate caches when those events occur. If that invalidation
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fails the region will fail to enable. Reasons for cache
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invalidation failure are due to the CPU not providing a cache
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invalidation mechanism. For example usage of wbinvd is restricted to
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bare metal x86. However, for testing purposes toggling this option
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can disable that data integrity safety and proceed with enabling
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regions when there might be conflicting contents in the CPU cache.
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If unsure, or if this kernel is meant for production environments,
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say N.
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endif
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