464 lines
16 KiB
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464 lines
16 KiB
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=====================
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Booting AArch64 Linux
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=====================
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Author: Will Deacon <will.deacon@arm.com>
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Date : 07 September 2012
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This document is based on the ARM booting document by Russell King and
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is relevant to all public releases of the AArch64 Linux kernel.
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The AArch64 exception model is made up of a number of exception levels
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(EL0 - EL3), with EL0, EL1 and EL2 having a secure and a non-secure
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counterpart. EL2 is the hypervisor level, EL3 is the highest priority
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level and exists only in secure mode. Both are architecturally optional.
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For the purposes of this document, we will use the term `boot loader`
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simply to define all software that executes on the CPU(s) before control
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is passed to the Linux kernel. This may include secure monitor and
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hypervisor code, or it may just be a handful of instructions for
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preparing a minimal boot environment.
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Essentially, the boot loader should provide (as a minimum) the
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following:
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1. Setup and initialise the RAM
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2. Setup the device tree
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3. Decompress the kernel image
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4. Call the kernel image
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1. Setup and initialise RAM
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---------------------------
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Requirement: MANDATORY
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The boot loader is expected to find and initialise all RAM that the
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kernel will use for volatile data storage in the system. It performs
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this in a machine dependent manner. (It may use internal algorithms
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to automatically locate and size all RAM, or it may use knowledge of
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the RAM in the machine, or any other method the boot loader designer
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sees fit.)
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2. Setup the device tree
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-------------------------
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Requirement: MANDATORY
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The device tree blob (dtb) must be placed on an 8-byte boundary and must
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not exceed 2 megabytes in size. Since the dtb will be mapped cacheable
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using blocks of up to 2 megabytes in size, it must not be placed within
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any 2M region which must be mapped with any specific attributes.
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NOTE: versions prior to v4.2 also require that the DTB be placed within
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the 512 MB region starting at text_offset bytes below the kernel Image.
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3. Decompress the kernel image
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------------------------------
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Requirement: OPTIONAL
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The AArch64 kernel does not currently provide a decompressor and
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therefore requires decompression (gzip etc.) to be performed by the boot
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loader if a compressed Image target (e.g. Image.gz) is used. For
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bootloaders that do not implement this requirement, the uncompressed
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Image target is available instead.
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4. Call the kernel image
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------------------------
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Requirement: MANDATORY
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The decompressed kernel image contains a 64-byte header as follows::
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u32 code0; /* Executable code */
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u32 code1; /* Executable code */
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u64 text_offset; /* Image load offset, little endian */
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u64 image_size; /* Effective Image size, little endian */
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u64 flags; /* kernel flags, little endian */
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u64 res2 = 0; /* reserved */
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u64 res3 = 0; /* reserved */
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u64 res4 = 0; /* reserved */
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u32 magic = 0x644d5241; /* Magic number, little endian, "ARM\x64" */
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u32 res5; /* reserved (used for PE COFF offset) */
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Header notes:
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- As of v3.17, all fields are little endian unless stated otherwise.
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- code0/code1 are responsible for branching to stext.
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- when booting through EFI, code0/code1 are initially skipped.
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res5 is an offset to the PE header and the PE header has the EFI
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entry point (efi_stub_entry). When the stub has done its work, it
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jumps to code0 to resume the normal boot process.
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- Prior to v3.17, the endianness of text_offset was not specified. In
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these cases image_size is zero and text_offset is 0x80000 in the
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endianness of the kernel. Where image_size is non-zero image_size is
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little-endian and must be respected. Where image_size is zero,
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text_offset can be assumed to be 0x80000.
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- The flags field (introduced in v3.17) is a little-endian 64-bit field
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composed as follows:
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============= ===============================================================
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Bit 0 Kernel endianness. 1 if BE, 0 if LE.
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Bit 1-2 Kernel Page size.
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* 0 - Unspecified.
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* 1 - 4K
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* 2 - 16K
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* 3 - 64K
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Bit 3 Kernel physical placement
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0
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2MB aligned base should be as close as possible
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to the base of DRAM, since memory below it is not
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accessible via the linear mapping
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1
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2MB aligned base such that all image_size bytes
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counted from the start of the image are within
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the 48-bit addressable range of physical memory
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Bits 4-63 Reserved.
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============= ===============================================================
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- When image_size is zero, a bootloader should attempt to keep as much
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memory as possible free for use by the kernel immediately after the
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end of the kernel image. The amount of space required will vary
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depending on selected features, and is effectively unbound.
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The Image must be placed text_offset bytes from a 2MB aligned base
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address anywhere in usable system RAM and called there. The region
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between the 2 MB aligned base address and the start of the image has no
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special significance to the kernel, and may be used for other purposes.
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At least image_size bytes from the start of the image must be free for
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use by the kernel.
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NOTE: versions prior to v4.6 cannot make use of memory below the
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physical offset of the Image so it is recommended that the Image be
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placed as close as possible to the start of system RAM.
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If an initrd/initramfs is passed to the kernel at boot, it must reside
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entirely within a 1 GB aligned physical memory window of up to 32 GB in
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size that fully covers the kernel Image as well.
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Any memory described to the kernel (even that below the start of the
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image) which is not marked as reserved from the kernel (e.g., with a
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memreserve region in the device tree) will be considered as available to
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the kernel.
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Before jumping into the kernel, the following conditions must be met:
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- Quiesce all DMA capable devices so that memory does not get
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corrupted by bogus network packets or disk data. This will save
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you many hours of debug.
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- Primary CPU general-purpose register settings:
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- x0 = physical address of device tree blob (dtb) in system RAM.
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- x1 = 0 (reserved for future use)
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- x2 = 0 (reserved for future use)
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- x3 = 0 (reserved for future use)
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- CPU mode
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All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
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IRQ and FIQ).
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The CPU must be in non-secure state, either in EL2 (RECOMMENDED in order
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to have access to the virtualisation extensions), or in EL1.
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- Caches, MMUs
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The MMU must be off.
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The instruction cache may be on or off, and must not hold any stale
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entries corresponding to the loaded kernel image.
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The address range corresponding to the loaded kernel image must be
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cleaned to the PoC. In the presence of a system cache or other
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coherent masters with caches enabled, this will typically require
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cache maintenance by VA rather than set/way operations.
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System caches which respect the architected cache maintenance by VA
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operations must be configured and may be enabled.
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System caches which do not respect architected cache maintenance by VA
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operations (not recommended) must be configured and disabled.
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- Architected timers
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CNTFRQ must be programmed with the timer frequency and CNTVOFF must
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be programmed with a consistent value on all CPUs. If entering the
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kernel at EL1, CNTHCTL_EL2 must have EL1PCTEN (bit 0) set where
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available.
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- Coherency
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All CPUs to be booted by the kernel must be part of the same coherency
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domain on entry to the kernel. This may require IMPLEMENTATION DEFINED
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initialisation to enable the receiving of maintenance operations on
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each CPU.
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- System registers
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All writable architected system registers at or below the exception
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level where the kernel image will be entered must be initialised by
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software at a higher exception level to prevent execution in an UNKNOWN
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state.
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For all systems:
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- If EL3 is present:
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- SCR_EL3.FIQ must have the same value across all CPUs the kernel is
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executing on.
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- The value of SCR_EL3.FIQ must be the same as the one present at boot
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time whenever the kernel is executing.
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- If EL3 is present and the kernel is entered at EL2:
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- SCR_EL3.HCE (bit 8) must be initialised to 0b1.
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For systems with a GICv3 interrupt controller to be used in v3 mode:
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- If EL3 is present:
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- ICC_SRE_EL3.Enable (bit 3) must be initialised to 0b1.
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- ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
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- ICC_CTLR_EL3.PMHE (bit 6) must be set to the same value across
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all CPUs the kernel is executing on, and must stay constant
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for the lifetime of the kernel.
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- If the kernel is entered at EL1:
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- ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1
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- ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.
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- The DT or ACPI tables must describe a GICv3 interrupt controller.
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For systems with a GICv3 interrupt controller to be used in
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compatibility (v2) mode:
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- If EL3 is present:
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ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b0.
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- If the kernel is entered at EL1:
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ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b0.
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- The DT or ACPI tables must describe a GICv2 interrupt controller.
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For CPUs with pointer authentication functionality:
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- If EL3 is present:
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- SCR_EL3.APK (bit 16) must be initialised to 0b1
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- SCR_EL3.API (bit 17) must be initialised to 0b1
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- If the kernel is entered at EL1:
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- HCR_EL2.APK (bit 40) must be initialised to 0b1
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- HCR_EL2.API (bit 41) must be initialised to 0b1
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For CPUs with Activity Monitors Unit v1 (AMUv1) extension present:
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- If EL3 is present:
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- CPTR_EL3.TAM (bit 30) must be initialised to 0b0
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- CPTR_EL2.TAM (bit 30) must be initialised to 0b0
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- AMCNTENSET0_EL0 must be initialised to 0b1111
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- AMCNTENSET1_EL0 must be initialised to a platform specific value
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having 0b1 set for the corresponding bit for each of the auxiliary
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counters present.
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- If the kernel is entered at EL1:
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- AMCNTENSET0_EL0 must be initialised to 0b1111
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- AMCNTENSET1_EL0 must be initialised to a platform specific value
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having 0b1 set for the corresponding bit for each of the auxiliary
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counters present.
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For CPUs with the Fine Grained Traps (FEAT_FGT) extension present:
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- If EL3 is present and the kernel is entered at EL2:
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- SCR_EL3.FGTEn (bit 27) must be initialised to 0b1.
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For CPUs with support for HCRX_EL2 (FEAT_HCX) present:
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- If EL3 is present and the kernel is entered at EL2:
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- SCR_EL3.HXEn (bit 38) must be initialised to 0b1.
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For CPUs with Advanced SIMD and floating point support:
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- If EL3 is present:
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- CPTR_EL3.TFP (bit 10) must be initialised to 0b0.
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- If EL2 is present and the kernel is entered at EL1:
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- CPTR_EL2.TFP (bit 10) must be initialised to 0b0.
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For CPUs with the Scalable Vector Extension (FEAT_SVE) present:
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- if EL3 is present:
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- CPTR_EL3.EZ (bit 8) must be initialised to 0b1.
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- ZCR_EL3.LEN must be initialised to the same value for all CPUs the
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kernel is executed on.
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- If the kernel is entered at EL1 and EL2 is present:
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- CPTR_EL2.TZ (bit 8) must be initialised to 0b0.
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- CPTR_EL2.ZEN (bits 17:16) must be initialised to 0b11.
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- ZCR_EL2.LEN must be initialised to the same value for all CPUs the
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kernel will execute on.
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For CPUs with the Scalable Matrix Extension (FEAT_SME):
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- If EL3 is present:
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- CPTR_EL3.ESM (bit 12) must be initialised to 0b1.
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- SCR_EL3.EnTP2 (bit 41) must be initialised to 0b1.
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- SMCR_EL3.LEN must be initialised to the same value for all CPUs the
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kernel will execute on.
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- If the kernel is entered at EL1 and EL2 is present:
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- CPTR_EL2.TSM (bit 12) must be initialised to 0b0.
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- CPTR_EL2.SMEN (bits 25:24) must be initialised to 0b11.
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- SCTLR_EL2.EnTP2 (bit 60) must be initialised to 0b1.
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- SMCR_EL2.LEN must be initialised to the same value for all CPUs the
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kernel will execute on.
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- HWFGRTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.
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- HWFGWTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.
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- HWFGRTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.
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- HWFGWTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.
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For CPUs with the Scalable Matrix Extension FA64 feature (FEAT_SME_FA64)
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- If EL3 is present:
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- SMCR_EL3.FA64 (bit 31) must be initialised to 0b1.
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- If the kernel is entered at EL1 and EL2 is present:
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- SMCR_EL2.FA64 (bit 31) must be initialised to 0b1.
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For CPUs with the Memory Tagging Extension feature (FEAT_MTE2):
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- If EL3 is present:
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- SCR_EL3.ATA (bit 26) must be initialised to 0b1.
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- If the kernel is entered at EL1 and EL2 is present:
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- HCR_EL2.ATA (bit 56) must be initialised to 0b1.
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For CPUs with the Scalable Matrix Extension version 2 (FEAT_SME2):
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- If EL3 is present:
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- SMCR_EL3.EZT0 (bit 30) must be initialised to 0b1.
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- If the kernel is entered at EL1 and EL2 is present:
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- SMCR_EL2.EZT0 (bit 30) must be initialised to 0b1.
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For CPUs with Memory Copy and Memory Set instructions (FEAT_MOPS):
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- If the kernel is entered at EL1 and EL2 is present:
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- HCRX_EL2.MSCEn (bit 11) must be initialised to 0b1.
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For CPUs with the Extended Translation Control Register feature (FEAT_TCR2):
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- If EL3 is present:
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- SCR_EL3.TCR2En (bit 43) must be initialised to 0b1.
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- If the kernel is entered at EL1 and EL2 is present:
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- HCRX_EL2.TCR2En (bit 14) must be initialised to 0b1.
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For CPUs with the Stage 1 Permission Indirection Extension feature (FEAT_S1PIE):
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- If EL3 is present:
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- SCR_EL3.PIEn (bit 45) must be initialised to 0b1.
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- If the kernel is entered at EL1 and EL2 is present:
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- HFGRTR_EL2.nPIR_EL1 (bit 58) must be initialised to 0b1.
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- HFGWTR_EL2.nPIR_EL1 (bit 58) must be initialised to 0b1.
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- HFGRTR_EL2.nPIRE0_EL1 (bit 57) must be initialised to 0b1.
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- HFGRWR_EL2.nPIRE0_EL1 (bit 57) must be initialised to 0b1.
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The requirements described above for CPU mode, caches, MMUs, architected
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timers, coherency and system registers apply to all CPUs. All CPUs must
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enter the kernel in the same exception level. Where the values documented
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disable traps it is permissible for these traps to be enabled so long as
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those traps are handled transparently by higher exception levels as though
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the values documented were set.
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The boot loader is expected to enter the kernel on each CPU in the
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following manner:
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- The primary CPU must jump directly to the first instruction of the
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kernel image. The device tree blob passed by this CPU must contain
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an 'enable-method' property for each cpu node. The supported
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enable-methods are described below.
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It is expected that the bootloader will generate these device tree
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properties and insert them into the blob prior to kernel entry.
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- CPUs with a "spin-table" enable-method must have a 'cpu-release-addr'
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property in their cpu node. This property identifies a
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naturally-aligned 64-bit zero-initalised memory location.
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These CPUs should spin outside of the kernel in a reserved area of
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memory (communicated to the kernel by a /memreserve/ region in the
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device tree) polling their cpu-release-addr location, which must be
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contained in the reserved region. A wfe instruction may be inserted
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to reduce the overhead of the busy-loop and a sev will be issued by
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the primary CPU. When a read of the location pointed to by the
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cpu-release-addr returns a non-zero value, the CPU must jump to this
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value. The value will be written as a single 64-bit little-endian
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value, so CPUs must convert the read value to their native endianness
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before jumping to it.
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- CPUs with a "psci" enable method should remain outside of
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the kernel (i.e. outside of the regions of memory described to the
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kernel in the memory node, or in a reserved area of memory described
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to the kernel by a /memreserve/ region in the device tree). The
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kernel will issue CPU_ON calls as described in ARM document number ARM
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DEN 0022A ("Power State Coordination Interface System Software on ARM
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processors") to bring CPUs into the kernel.
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The device tree should contain a 'psci' node, as described in
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Documentation/devicetree/bindings/arm/psci.yaml.
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- Secondary CPU general-purpose register settings
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- x0 = 0 (reserved for future use)
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- x1 = 0 (reserved for future use)
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- x2 = 0 (reserved for future use)
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- x3 = 0 (reserved for future use)
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