97 lines
2.6 KiB
C
97 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2016-2018 Xilinx
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*/
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#ifndef __LINUX_CLK_ZYNQMP_H_
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#define __LINUX_CLK_ZYNQMP_H_
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#include <linux/spinlock.h>
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#include <linux/firmware/xlnx-zynqmp.h>
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/* Common Flags */
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/* must be gated across rate change */
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#define ZYNQMP_CLK_SET_RATE_GATE BIT(0)
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/* must be gated across re-parent */
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#define ZYNQMP_CLK_SET_PARENT_GATE BIT(1)
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/* propagate rate change up one level */
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#define ZYNQMP_CLK_SET_RATE_PARENT BIT(2)
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/* do not gate even if unused */
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#define ZYNQMP_CLK_IGNORE_UNUSED BIT(3)
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/* don't re-parent on rate change */
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#define ZYNQMP_CLK_SET_RATE_NO_REPARENT BIT(7)
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/* do not gate, ever */
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#define ZYNQMP_CLK_IS_CRITICAL BIT(11)
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/* Type Flags for divider clock */
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#define ZYNQMP_CLK_DIVIDER_ONE_BASED BIT(0)
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#define ZYNQMP_CLK_DIVIDER_POWER_OF_TWO BIT(1)
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#define ZYNQMP_CLK_DIVIDER_ALLOW_ZERO BIT(2)
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#define ZYNQMP_CLK_DIVIDER_HIWORD_MASK BIT(3)
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#define ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST BIT(4)
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#define ZYNQMP_CLK_DIVIDER_READ_ONLY BIT(5)
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#define ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO BIT(6)
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/* Type Flags for mux clock */
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#define ZYNQMP_CLK_MUX_INDEX_ONE BIT(0)
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#define ZYNQMP_CLK_MUX_INDEX_BIT BIT(1)
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#define ZYNQMP_CLK_MUX_HIWORD_MASK BIT(2)
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#define ZYNQMP_CLK_MUX_READ_ONLY BIT(3)
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#define ZYNQMP_CLK_MUX_ROUND_CLOSEST BIT(4)
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#define ZYNQMP_CLK_MUX_BIG_ENDIAN BIT(5)
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enum topology_type {
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TYPE_INVALID,
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TYPE_MUX,
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TYPE_PLL,
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TYPE_FIXEDFACTOR,
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TYPE_DIV1,
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TYPE_DIV2,
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TYPE_GATE,
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};
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/**
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* struct clock_topology - Clock topology
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* @type: Type of topology
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* @flag: Topology flags
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* @type_flag: Topology type specific flag
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*/
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struct clock_topology {
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u32 type;
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u32 flag;
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u32 type_flag;
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u8 custom_type_flag;
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};
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unsigned long zynqmp_clk_map_common_ccf_flags(const u32 zynqmp_flag);
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struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,
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const char * const *parents,
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u8 num_parents,
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const struct clock_topology *nodes);
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struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id,
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const char * const *parents,
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u8 num_parents,
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const struct clock_topology *nodes);
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struct clk_hw *zynqmp_clk_register_divider(const char *name,
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u32 clk_id,
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const char * const *parents,
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u8 num_parents,
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const struct clock_topology *nodes);
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struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id,
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const char * const *parents,
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u8 num_parents,
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const struct clock_topology *nodes);
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struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name,
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u32 clk_id,
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const char * const *parents,
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u8 num_parents,
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const struct clock_topology *nodes);
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#endif
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