83 lines
		
	
	
		
			2.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			83 lines
		
	
	
		
			2.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /* SPDX-License-Identifier: GPL-2.0+ */
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| /* Copyright (c) 2015-2016 Quantenna Communications */
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| 
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| #ifndef _QTN_FMAC_PCIE_IPC_H_
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| #define _QTN_FMAC_PCIE_IPC_H_
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| 
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| #include <linux/types.h>
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| 
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| #include "shm_ipc_defs.h"
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| 
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| /* bitmap for EP status and flags: updated by EP, read by RC */
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| #define QTN_EP_HAS_UBOOT	BIT(0)
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| #define QTN_EP_HAS_FIRMWARE	BIT(1)
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| #define QTN_EP_REQ_UBOOT	BIT(2)
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| #define QTN_EP_REQ_FIRMWARE	BIT(3)
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| #define QTN_EP_ERROR_UBOOT	BIT(4)
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| #define QTN_EP_ERROR_FIRMWARE	BIT(5)
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| 
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| #define QTN_EP_FW_LOADRDY	BIT(8)
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| #define QTN_EP_FW_SYNC		BIT(9)
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| #define QTN_EP_FW_RETRY		BIT(10)
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| #define QTN_EP_FW_QLINK_DONE	BIT(15)
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| #define QTN_EP_FW_DONE		BIT(16)
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| 
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| /* bitmap for RC status and flags: updated by RC, read by EP */
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| #define QTN_RC_PCIE_LINK	BIT(0)
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| #define QTN_RC_NET_LINK		BIT(1)
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| #define QTN_RC_FW_FLASHBOOT	BIT(5)
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| #define QTN_RC_FW_QLINK		BIT(7)
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| #define QTN_RC_FW_LOADRDY	BIT(8)
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| #define QTN_RC_FW_SYNC		BIT(9)
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| 
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| #define PCIE_HDP_INT_RX_BITS (0		\
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| 	| PCIE_HDP_INT_EP_TXDMA		\
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| 	| PCIE_HDP_INT_EP_TXEMPTY	\
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| 	| PCIE_HDP_INT_HHBM_UF		\
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| 	)
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| 
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| #define PCIE_HDP_INT_TX_BITS (0		\
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| 	| PCIE_HDP_INT_EP_RXDMA		\
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| 	)
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| 
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| #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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| #define QTN_HOST_HI32(a)	((u32)(((u64)a) >> 32))
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| #define QTN_HOST_LO32(a)	((u32)(((u64)a) & 0xffffffffUL))
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| #define QTN_HOST_ADDR(h, l)	((((u64)h) << 32) | ((u64)l))
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| #else
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| #define QTN_HOST_HI32(a)	0
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| #define QTN_HOST_LO32(a)	((u32)(((u32)a) & 0xffffffffUL))
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| #define QTN_HOST_ADDR(h, l)	((u32)l)
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| #endif
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| 
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| #define QTN_PCIE_BDA_VERSION		0x1002
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| 
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| #define PCIE_BDA_NAMELEN		32
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| #define PCIE_HHBM_MAX_SIZE		2048
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| 
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| #define QTN_PCIE_BOARDFLG	"PCIEQTN"
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| #define QTN_PCIE_FW_DLMASK	0xF
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| #define QTN_PCIE_FW_BUFSZ	2048
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| 
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| #define QTN_ENET_ADDR_LENGTH	6
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| 
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| #define QTN_TXDONE_MASK		((u32)0x80000000)
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| #define QTN_GET_LEN(x)		((x) & 0xFFFF)
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| 
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| #define QTN_PCIE_TX_DESC_LEN_MASK	0xFFFF
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| #define QTN_PCIE_TX_DESC_LEN_SHIFT	0
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| #define QTN_PCIE_TX_DESC_PORT_MASK	0xF
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| #define QTN_PCIE_TX_DESC_PORT_SHIFT	16
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| #define QTN_PCIE_TX_DESC_TQE_BIT	BIT(24)
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| 
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| #define QTN_EP_LHOST_TQE_PORT	4
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| 
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| enum qtnf_fw_loadtype {
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| 	QTN_FW_DBEGIN,
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| 	QTN_FW_DSUB,
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| 	QTN_FW_DEND,
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| 	QTN_FW_CTRL
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| };
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| 
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| #endif /* _QTN_FMAC_PCIE_IPC_H_ */
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