kernel/Documentation/devicetree/bindings/fpga
2025-07-14 21:16:13 +00:00
..
altera-fpga2sdram-bridge.txt Initial import of 5.14.0-570.25.1.el9_6 2025-07-14 21:16:13 +00:00
altera-freeze-bridge.txt Initial import of 5.14.0-570.25.1.el9_6 2025-07-14 21:16:13 +00:00
altera-hps2fpga-bridge.txt Initial import of 5.14.0-570.25.1.el9_6 2025-07-14 21:16:13 +00:00
altera-passive-serial.txt Initial import of 5.14.0-570.25.1.el9_6 2025-07-14 21:16:13 +00:00
altera-pr-ip.txt Initial import of 5.14.0-570.25.1.el9_6 2025-07-14 21:16:13 +00:00
altera-socfpga-a10-fpga-mgr.txt Initial import of 5.14.0-570.25.1.el9_6 2025-07-14 21:16:13 +00:00
altera-socfpga-fpga-mgr.txt Initial import of 5.14.0-570.25.1.el9_6 2025-07-14 21:16:13 +00:00
fpga-bridge.txt Initial import of 5.14.0-570.25.1.el9_6 2025-07-14 21:16:13 +00:00
fpga-region.txt Initial import of 5.14.0-570.25.1.el9_6 2025-07-14 21:16:13 +00:00
intel-stratix10-soc-fpga-mgr.txt Initial import of 5.14.0-570.25.1.el9_6 2025-07-14 21:16:13 +00:00
lattice-ice40-fpga-mgr.txt Initial import of 5.14.0-570.25.1.el9_6 2025-07-14 21:16:13 +00:00
lattice-machxo2-spi.txt Initial import of 5.14.0-570.25.1.el9_6 2025-07-14 21:16:13 +00:00
xilinx-pr-decoupler.txt Initial import of 5.14.0-570.25.1.el9_6 2025-07-14 21:16:13 +00:00
xilinx-slave-serial.txt Initial import of 5.14.0-570.25.1.el9_6 2025-07-14 21:16:13 +00:00
xilinx-zynq-fpga-mgr.yaml Initial import of 5.14.0-570.25.1.el9_6 2025-07-14 21:16:13 +00:00
xlnx,zynqmp-pcap-fpga.txt Initial import of 5.14.0-570.25.1.el9_6 2025-07-14 21:16:13 +00:00