40 lines
838 B
C
40 lines
838 B
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2024 Intel Corporation
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*/
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#include "i915_drv.h"
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#include "intel_gt.h"
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#include "intel_gt_ccs_mode.h"
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#include "intel_gt_regs.h"
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unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt)
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{
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int cslice;
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u32 mode = 0;
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int first_ccs = __ffs(CCS_MASK(gt));
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if (!IS_DG2(gt->i915))
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return 0;
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/* Build the value for the fixed CCS load balancing */
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for (cslice = 0; cslice < I915_MAX_CCS; cslice++) {
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if (gt->ccs.cslices & BIT(cslice))
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/*
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* If available, assign the cslice
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* to the first available engine...
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*/
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mode |= XEHP_CCS_MODE_CSLICE(cslice, first_ccs);
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else
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/*
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* ... otherwise, mark the cslice as
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* unavailable if no CCS dispatches here
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*/
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mode |= XEHP_CCS_MODE_CSLICE(cslice,
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XEHP_CCS_MODE_CSLICE_MASK);
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}
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return mode;
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}
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