113 lines
3.2 KiB
C
113 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0 OR MIT
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/*
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* Copyright 2023 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <linux/dma-fence.h>
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#include <linux/workqueue.h>
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#include "amdgpu.h"
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#include "amdgpu_vm.h"
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#include "amdgpu_gmc.h"
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struct amdgpu_tlb_fence {
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struct dma_fence base;
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struct amdgpu_device *adev;
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struct dma_fence *dependency;
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struct work_struct work;
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spinlock_t lock;
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uint16_t pasid;
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};
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static const char *amdgpu_tlb_fence_get_driver_name(struct dma_fence *fence)
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{
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return "amdgpu tlb fence";
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}
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static const char *amdgpu_tlb_fence_get_timeline_name(struct dma_fence *f)
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{
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return "amdgpu tlb timeline";
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}
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static void amdgpu_tlb_fence_work(struct work_struct *work)
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{
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struct amdgpu_tlb_fence *f = container_of(work, typeof(*f), work);
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int r;
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if (f->dependency) {
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dma_fence_wait(f->dependency, false);
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dma_fence_put(f->dependency);
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f->dependency = NULL;
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}
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r = amdgpu_gmc_flush_gpu_tlb_pasid(f->adev, f->pasid, 2, true, 0);
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if (r) {
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dev_err(f->adev->dev, "TLB flush failed for PASID %d.\n",
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f->pasid);
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dma_fence_set_error(&f->base, r);
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}
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dma_fence_signal(&f->base);
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dma_fence_put(&f->base);
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}
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static const struct dma_fence_ops amdgpu_tlb_fence_ops = {
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.use_64bit_seqno = true,
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.get_driver_name = amdgpu_tlb_fence_get_driver_name,
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.get_timeline_name = amdgpu_tlb_fence_get_timeline_name
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};
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void amdgpu_vm_tlb_fence_create(struct amdgpu_device *adev, struct amdgpu_vm *vm,
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struct dma_fence **fence)
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{
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struct amdgpu_tlb_fence *f;
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f = kmalloc(sizeof(*f), GFP_KERNEL);
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if (!f) {
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/*
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* We can't fail since the PDEs and PTEs are already updated, so
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* just block for the dependency and execute the TLB flush
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*/
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if (*fence)
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dma_fence_wait(*fence, false);
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amdgpu_gmc_flush_gpu_tlb_pasid(adev, vm->pasid, 2, true, 0);
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*fence = dma_fence_get_stub();
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return;
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}
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f->adev = adev;
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f->dependency = *fence;
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f->pasid = vm->pasid;
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INIT_WORK(&f->work, amdgpu_tlb_fence_work);
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spin_lock_init(&f->lock);
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dma_fence_init(&f->base, &amdgpu_tlb_fence_ops, &f->lock,
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vm->tlb_fence_context, atomic64_read(&vm->tlb_seq));
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/* TODO: We probably need a separate wq here */
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dma_fence_get(&f->base);
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schedule_work(&f->work);
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*fence = &f->base;
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}
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